Rafael C Camarota

6418045, Jul 9, 2002

Jun 28, 2001

09/896406

Rafael C. Camarota - Sunnyvale CA

Adaptive Silicon, Inc. - Los Gatos CA

G11C 1100

365156, 365154

For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.

6462576, Oct 8, 2002

Sep 14, 2000

09/661585

Albert Chan - Palo Alto CA
Ju Shen - Saratoga CA
Cyrus Y. Tsui - Los Altos Hills CA
Rafael C. Camarota - Sunnyvale CA

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19177

326 39, 326 47

An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of either the first or the second product term summing circuit.

6744274, Jun 1, 2004

Jul 26, 2002

10/206872

Jeffrey M. Arnold - San Diego CA
Rafael C. Camarota - Sunnyvale CA
Joseph H. Hassoun - Los Gatos CA
Charle R. Rupp - Morgan Hill CA

Stretch, Inc. - Mountain View CA

H03K 19177

326 16, 326 39, 326 40, 326 41, 714724

A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.

7023238, Apr 4, 2006

Jan 7, 2004

10/753585

Rafael C. Camarota - Sunnyvale CA, US

Altera Corporation - San Jose CA

H03K 19/173
G06F 7/38

326 38, 326 40, 327205

An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

7154297, Dec 26, 2006

Jan 21, 2005

10/905832

Rafael C. Camarota - Sunnyvale CA, US
Robert Blake - Saratoga CA, US

Altera Corporation - San Jose CA

H03K 19/177
G06F 7/38

326 40, 326 38, 716 17

Volatility of a programmable logic device (PLD) or field programmable gate array (FPGA) is selectable to be volatile or nonvolatile. In the volatile mode, configuration or other data of the integrated circuit are lost once power is removed from the integrated circuit. In the nonvolatile mode, configuration or other data is retained even when power is removed from the integrated circuit. Upon power-up, in nonvolatile mode, the integrated circuit does not need external data. In an embodiment, the mode, whether volatile or nonvolatile, may be selected during manufacturing. In other embodiment, the mode may be selected by other means, such as by the user.

7190190, Mar 13, 2007

Jan 9, 2004

10/754432

Rafael C. Camarota - Sunnyvale CA, US
Tom White - Santa Clara CA, US

Altera Corporation - San Jose CA

H03K 19/173
H03K 19/177
G06F 7/38
H01L 25/00

326 38, 326 37, 326 39, 326 40, 326 41, 326 47, 716 16

A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

7242218, Jul 10, 2007

Dec 2, 2004

11/003586

Rafael Camarota - Sunnyvale CA, US
Irfan Rahim - San Jose CA, US
Boon Jin Ang - Penang, MY
Thow Pang Chong - Johor, MY

Altera Corporation - San Jose CA

H03K 19/173
H03K 19/177
G06F 7/38
H01L 25/00

326 41, 326 37, 326 38, 326 39, 326 40, 326 47, 716 16, 710100, 710104, 710131

Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

7248070, Jul 24, 2007

Feb 16, 2005

11/059929

Patrick Guilloteau - Palaiseau, FR
Rafael C. Camarota - Sunnyvale CA, US
Arun Kumar Varadarajan Rajagopal - San Francisco CA, US

Altera Corporation - San Jose CA

H03K 19/173

326 38, 714726

A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.