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Prashant B Phatak

from San Jose, CA
Age ~58

Prashant Phatak Phones & Addresses

  • 1052 Bentoak Ln, San Jose, CA 95129 (408) 221-4016
  • 1052 Eugene Ave, San Jose, CA 95126
  • 592 Crystalberry Ter, San Jose, CA 95129
  • Sunnyvale, CA
  • Santa Clara, CA
  • Berkeley, CA
  • 1052 Bentoak Ln, San Jose, CA 95129 (408) 406-6498

Resumes

Resumes

Prashant Phatak Photo 1

Technologist

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Intermolecular Inc since Jan 2008
Technology Director

Intermolecular Inc Oct 2006 - Dec 2007
Program Manager

Cypress Semiconductor Oct 2005 - Oct 2006
Process technology Manager

Cypress Semiconductor Apr 1998 - Sep 2005
Process development

University Of California 1996 - 1998
Integrated Materials Laboratory Manager
Education:
University of California, Berkeley 1988 - 1995
Indian Institute of Technology, Kanpur 1984 - 1988
Skills:
Silicon
Materials
Cmos
Design of Experiments
Manufacturing
Research
Characterization
R&D
Materials Science
Engineering Management
Semiconductor Industry
Failure Analysis
Cross Functional Team Leadership
Research and Development
Process Simulation
Semiconductor Manufacturing
Statistics
Thin Films
Nanotechnology
Creative Problem Solving
Integrated Circuits
Memory
Mems
Process Integration
Spc
Ic
Languages:
Marathi
Hindi
Prashant Phatak Photo 2

Prashant Phatak

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Prashant Phatak Photo 3

Prashant Phatak

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Publications

Us Patents

Multi-Step High Density Plasma (Hdp) Process To Obtain Uniformly Doped Insulating Film

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US Patent:
6852649, Feb 8, 2005
Filed:
Mar 30, 2001
Appl. No.:
09/823839
Inventors:
Prashant B. Phatak - Sunnyvale CA, US
Michal Fastow - Cupertino CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L021/31
H01L021/469
US Classification:
438783, 438778, 438784, 438787
Abstract:
A method of forming an essentially uniform doped insulating layer is disclosed. Variations in a substrate temperature that may result in a dopant gradient within a doped insulating layer can be compensated for by varying a dopant supply rate in a deposition process. One particular embodiment discloses a method of forming a high density plasma phosphosilicate glass having a phosphorous concentration of 8% or greater by weight that varies by no more than about 1% by weight throughout.

Methods For Forming Nonvolatile Memory Elements With Resistive-Switching Metal Oxides

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US Patent:
7629198, Dec 8, 2009
Filed:
Mar 5, 2007
Appl. No.:
11/714334
Inventors:
Nitin Kumar - Menlo Park CA, US
Jinhong Tong - Santa Clara CA, US
Chi-I Lang - Sunnyvale CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
H01L 21/16
US Classification:
438104, 438678, 257 4, 365 51
Abstract:
Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Methods Of Combinatorial Processing For Screening Multiple Samples On A Semiconductor Substrate

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US Patent:
7824935, Nov 2, 2010
Filed:
Jul 2, 2008
Appl. No.:
12/167118
Inventors:
Gaurav Verma - Sunnyvale CA, US
Kurt Weiner - San Jose CA, US
Prashant Phatak - San Jose CA, US
Imran Hashim - Saratoga CA, US
Sandra Malhotra - San Jose CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438 18, 257E21008
Abstract:
In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Confinement Techniques For Non-Volatile Resistive-Switching Memories

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US Patent:
7960216, Jun 14, 2011
Filed:
May 8, 2009
Appl. No.:
12/463174
Inventors:
Prashant Phatak - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/332
US Classification:
438133, 257 2, 257 4, 438381
Abstract:
Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.

Titanium-Based High-K Dielectric Films

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US Patent:
7968452, Jun 28, 2011
Filed:
Jun 30, 2009
Appl. No.:
12/494702
Inventors:
Hanhong Chen - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sunil Shanker - Santa Clara CA, US
Edward Haywood - San Jose CA, US
Sandra Malhotra - San Jose CA, US
Imran Hashim - Saratoga CA, US
Nobi Fuchigami - Santa Clara CA, US
Prashant Phatak - San Jose CA, US
Monica Mathur - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/4763
US Classification:
438635, 438381, 438399, 438584, 438591, 438656, 438680, 427123, 42724919, 42725532, 42725507, 257E2109
Abstract:
This disclosure provides (a) methods of making an oxide layer (e. g. , a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiOdielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiOdielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

Non-Volatile Resistive-Switching Memories Formed Using Anodization

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US Patent:
7977152, Jul 12, 2011
Filed:
May 8, 2009
Appl. No.:
12/463319
Inventors:
Alexander Gorer - Los Gatos CA, US
Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US
Igor Ivanov - Danville CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438104, 257E21175
Abstract:
Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Ald Processing Techniques For Forming Non-Volatile Resistive-Switching Memories

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US Patent:
8008096, Aug 30, 2011
Filed:
Jun 4, 2009
Appl. No.:
12/478680
Inventors:
Nobi Fuchigami - Santa Clara CA, US
Pragati Kumar - Santa Clara CA, US
Prashant Phatak - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438 3, 438257, 438785, 257E2168
Abstract:
ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100 Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

Stress-Engineered Resistance-Change Memory Device

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US Patent:
8049305, Nov 1, 2011
Filed:
Oct 15, 2009
Appl. No.:
12/580196
Inventors:
Michael Miller - San Jose CA, US
Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 29/10
US Classification:
257537, 257 30, 257 43, 257538, 257E27047
Abstract:
A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.
Prashant B Phatak from San Jose, CA, age ~58 Get Report