Peter Mark Fiacco

6829660, Dec 7, 2004

Dec 10, 2002

10/316604

Michael Liu - Alhambra CA
Bradley Roach - Newport Beach CA
Sam Su - Irvine CA
Peter Fiacco - Yorba Linda CA

Emulex Design Manufacturing Corporation - Costa Mesa CA

G06F 1328

710 22, 710 38, 710305, 709212

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

7096296, Aug 22, 2006

Nov 22, 2004

10/995456

Michael Liu - Alhambra CA, US
Bradley Roach - Newport Beach CA, US
Sam Su - Irvine CA, US
Peter Fiacco - Yorba Linda CA, US

Emulex Design & Manufacturing Corporation - Costa Mesa CA

G06F 13/24
G06F 13/32

710260, 710 15, 710 18, 710 19, 710 48, 710 52, 710261, 710263, 710267

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

7937188, May 3, 2011

May 23, 2007

11/805581

Michael Yu Liu - Costa Mesa CA, US
Bradley Eugene Roach - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US
Peter Mark Fiacco - Costa Mesa CA, US
Shak Loong Kwok - Costa Mesa CA, US

Emulex Design & Manufacturing Corporation - Costa Mesa CA

G06F 15/00

700299, 710 10, 702132, 713300, 709221

Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.

8631169, Jan 14, 2014

Jun 6, 2008

12/134985

Daming Jin - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US
Sam Shan-Jan Su - Costa Mesa CA, US
John Sui-Kei Tang - Costa Mesa CA, US
Peter Mark Fiacco - Costa Mesa CA, US

Emulex Design & Manufacturing Corporation - Costa Mesa CA

G06F 13/28

710 22

Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

7363396, Apr 22, 2008

Feb 24, 2006

11/361344

Michael Liu - Alhambra CA, US
Bradley Roach - Newport Beach CA, US
Sam Su - Irvine CA, US
Peter Fiacco - Yorba Linda CA, US

Emulex Design & Manufacturing Corporation - Costa Mesa CA

G06F 13/12
G06F 3/00
G06F 13/28

710 20, 710 1, 710 5, 710 21, 710 22, 710 29, 710 36, 710 38, 710 62, 710 72, 710305, 710306, 710308, 710311, 700 1, 700 2, 700 4, 709206, 709207, 709212, 709213, 709217, 709250

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

58601490, Jan 12, 1999

Jun 7, 1995

8/484592

Peter Fiacco - Yorba Linda CA
Wayne Rickard - Oceanside CA
Vi Chau - Laguna Niguel CA

Emulex Corporation - Costa Mesa CA

G06F 1206

711209

A partitioned memory is divided into a number of large buffers, and one or more of the large buffers is divided to create an equal number of small buffers. Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

57457271, Apr 28, 1998

Apr 15, 1997

8/843315

Vi Chau - Laguna Niguel CA
Stuart Berman - Newport Beach CA
Peter Fiacco - Yorba Linda CA

Emulex Corporation - Costa Mesa CA

G06F 1208

395449

A method and apparatus for linking two independent caches which have related information stored therein. Each unit of information stored in a first cache memory is associated with one unit of information stored in the second cache memory. Each unit of information stored in the first cache memory includes a pointer or index to the associated information unit in the second cache memory. Each information unit stored in the second cache is only stored once, regardless of the number of units in the first cache that are associated with a particular unit within the second cache. Therefore, even if more than one unit of information within the first cache memory is associated with the same unit of information within the second cache memory, that unit of information stored in the second cache memory is only stored once.

60413972, Mar 21, 2000

Jan 12, 1999

9/229464

Wayne Rickard - Oceanside CA
Peter Fiacco - Yorba Linda CA
Vi Chau - Laguna Niguel CA

Emulex Corporation - Costa Mesa CA

G06F 1200

711209

A system is configured to provide an efficient management or control of a buffer memory system. The system can also be used to transmit data between communicating components of a computer system. A first-in-first-out memory stores a list of buffer pointers, and control logic returns buffer pointers from the transmit registers, and moves buffer pointers to the bottom of the FIFO memory.