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Peter W Deelman

from Calabasas, CA
Age ~58

Peter Deelman Phones & Addresses

  • 23115 Blue Bird Dr, Calabasas, CA 91302 (818) 644-1002 (818) 222-1094
  • 5490 Duguid Rd, Fayetteville, NY 13066 (315) 637-9377
  • 102 Margo Ln, Fayetteville, NY 13066 (315) 637-9377
  • 11640 Woodbridge St, Studio City, CA 91604 (818) 623-7719
  • Wappingers Falls, NY
  • Pasadena, CA
  • Los Angeles, CA
  • East Greenbush, NY
  • 23115 Blue Bird Dr, Calabasas, CA 91302

Work

Position: Craftsman/Blue Collar

Education

Degree: High school graduate or higher

Publications

Us Patents

Method And Device For Growing Pseudomorphic Alinassb On Inas

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US Patent:
7598158, Oct 6, 2009
Filed:
Jun 5, 2006
Appl. No.:
11/447338
Inventors:
Peter Deelman - Calabasas CA, US
Ken Elliott - Thousand Oaks CA, US
David Chow - Newbury Park CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/20
US Classification:
438478, 257 15, 257E29072
Abstract:
A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

Thermal Management Substrate

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US Patent:
7695564, Apr 13, 2010
Filed:
Feb 3, 2005
Appl. No.:
11/051749
Inventors:
Miroslav Micovic - Thousand Oaks CA, US
Peter Deelman - Calabasas CA, US
Yakov Royter - Santa Monica CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
C30B 25/02
US Classification:
117 95, 117 9, 117 92, 117 97, 117103, 117108, 438423, 438480, 438766, 438514, 438516, 257E21005, 257E21041, 257E21049, 257E21095, 257E21096
Abstract:
The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

Fabricating A Device With A Diamond Layer

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US Patent:
7892881, Feb 22, 2011
Filed:
Feb 23, 2009
Appl. No.:
12/390593
Inventors:
Mary Y. Chen - Oak Park CA, US
Peter W. Deelman - Calabasas CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L 21/00
US Classification:
438105, 257 77, 257E21005
Abstract:
In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.

Method And Device For Growing Pseudomorphic Alinassb On Inas

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US Patent:
7968435, Jun 28, 2011
Filed:
Jun 24, 2009
Appl. No.:
12/491004
Inventors:
Peter Deelman - Calabasas CA, US
Ken Elliott - Thousand Oaks CA, US
David Chow - Newbury Park CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/20
US Classification:
438483, 438478, 438604, 257E29072, 257E29089
Abstract:
A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

Method And Device For Growing Pseudomorphic A1Inassb On Inas

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US Patent:
8242538, Aug 14, 2012
Filed:
May 11, 2011
Appl. No.:
13/105668
Inventors:
Peter Deelman - Calabasas CA, US
Ken Elliott - Thousand Oaks CA, US
David Chow - Newbury Park CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 31/102
US Classification:
257189, 257190, 257E33008, 257E33031, 257E31022
Abstract:
A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

Semiconductor Device Coding Using Quantum Dot Technology

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US Patent:
8595654, Nov 26, 2013
Filed:
Oct 3, 2006
Appl. No.:
11/542814
Inventors:
Mary Y. Chen - Oak Park CA, US
Peter W. Deelman - Calabasas CA, US
Marko Sokolich - Los Angeles CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
G06F 17/50
US Classification:
716 50, 716 51
Abstract:
Semiconductor device identification using quantum dot technology. A semiconductor nanocrystal based target is fabricated. A guard ring superjacent the fluorescing surface of the nanocrystal surface is provided to ensure repeatability of spectral mapping and analysis data. A transparent cap on the target may enhance performance. A system for coding a semiconductor device is described. A method is described for fabricating quantum dot targets in a methodology compatible with subsequent semiconductor fabrication process steps.

Gan Dhfet

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US Patent:
20040238842, Dec 2, 2004
Filed:
Apr 26, 2004
Appl. No.:
10/832691
Inventors:
Miroslav Micovic - Newbury Park CA, US
Tahir Hussain - Calabasas CA, US
Paul Hashimoto - Los Angeles CA, US
Peter Deelman - Calabasas CA, US
Assignee:
HRL Laboratories, LLC
International Classification:
H01L031/0328
US Classification:
257/192000
Abstract:
The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising AlGaN. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.
Peter W Deelman from Calabasas, CA, age ~58 Get Report