Search

Peeyush Purohit

from Portland, OR
Get Report
Related to:
Asha Purohit
Connected to:
Ajay Purohit, 64Akanksha Purohit, 39Aseem Purohit, 56Atmun A Purohit, 39Bhawana Purohit, 38Bijal K Purohit, 66Divyesh M Purohit, 110Gaurav D Purohit, 37Hemal M Purohit, 51Hemanshu R Purohit, 53

Peeyush Purohit Phones & Addresses

  • 2413 NW Byrne Ter, Portland, OR 97229
  • Hillsboro, OR

Work

Company: Qualcomm May 2014 to Mar 2016 Position: Qualcomm

Education

Degree: Bachelor of Engineering, Bachelors School / High School: Devi Ahilya Vishwavidyalaya 1995 to 1999 Specialities: Electronics

Skills

Vlsi • Verilog • Asic • Soc • Debugging • Systemverilog • Rtl Design • Embedded Systems • Semiconductors • Functional Verification • Ic

Industries

Semiconductors

Resumes

Resumes

Peeyush Purohit Photo 1

Director

View page
Location:
Portland, OR
Industry:
Semiconductors
Work:
Qualcomm May 2014 - Mar 2016
Qualcomm
Stmicroelectronics India 2003 - 2004
Design Engineer
Portalplayer, Inc. 2001 - 2003
Asic Design Engineer
Portalplayer 2001 - 2003
Design Engineer
Intel Corporation 2001 - 2003
Director
Education:
Devi Ahilya Vishwavidyalaya 1995 - 1999
Bachelor of Engineering, Bachelors, Electronics University of Mumbai
Masters, Master of Engineering, Engineering
Skills:
Vlsi
Verilog
Asic
Soc
Debugging
Systemverilog
Rtl Design
Embedded Systems
Semiconductors
Functional Verification
Ic

Publications

Us Patents

System, Method And Apparatus For Reducing Latency Of Receiver Operations During A Containment Mode Of Operation

View page
US Patent:
20230020359, Jan 19, 2023
Filed:
Sep 28, 2022
Appl. No.:
17/954419
Inventors:
Nitish Paliwal - Hillsboro OR, US
Binal Nasit - Cumming GA, US
Peeyush Purohit - Portland OR, US
Kirk S. Yap - Westborough MA, US
Raghunandan Makaram - Northborough MA, US
Robert G. Blankenship - Tacoma WA, US
International Classification:
G06F 21/60
G06F 21/62
G06F 21/85
Abstract:
In one embodiment, an apparatus includes: a control circuit to receive a message authentication code (MAC) for an epoch comprising a plurality of flits; a calculation circuit to calculate a computed MAC for the epoch; a cryptographic circuit to receive the epoch via a link and decrypt the plurality of flits, prior to authentication of the epoch; and at least one memory to store messages of the decrypted plurality of flits, prior to the authentication of the epoch. Other embodiments are described and claimed.

System, Apparatus And Method For Handling Multi-Protocol Traffic In Data Link Layer Circuitry

View page
US Patent:
20210112132, Apr 15, 2021
Filed:
Dec 21, 2020
Appl. No.:
17/128648
Inventors:
NITISH PALIWAL - Hillsboro OR, US
PEEYUSH PUROHIT - Portland OR, US
SWADESH CHOUDHARY - Mountain View CA, US
MANJULA PEDDIREDDY - Santa Clara CA, US
MAHESH NATU - Folsom CA, US
MAHESH WAGH - Portland OR, US
International Classification:
H04L 29/08
H04L 12/741
H04L 12/863
Abstract:
In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

High Bandwidth Link Layer For Coherent Messages

View page
US Patent:
20200334179, Oct 22, 2020
Filed:
Apr 3, 2020
Appl. No.:
16/840266
Inventors:
- Santa Clara CA, US
Peeyush Purohit - Portland OR, US
Nitish Paliwal - Hillsboro OR, US
Archana Srinivasan - Newark CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/16
G06F 11/10
G06F 13/42
G06F 13/40
Abstract:
Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

High Bandwidth Link Layer For Coherent Messages

View page
US Patent:
20190095363, Mar 28, 2019
Filed:
Sep 25, 2018
Appl. No.:
16/141729
Inventors:
- Santa Clara CA, US
Peeyush Purohit - Portland OR, US
Nitish Paliwal - Hillsboro OR, US
Archana Srinivasan - Newark CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/16
G06F 13/42
G06F 11/10
Abstract:
Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
Control profile
Peeyush Purohit from Portland, OR Get Report