Paul R Wensley

6440759, Aug 27, 2002

Jun 29, 2001

09/893475

Martin Commons - Stormville NY
Tobias Mono - Dresden, DE
Velt Klee - Pleasant Valley NY
John Pohl - Stoneygate, GB
Paul Wensley - Poughquag NY

Infineon Technologies AG - Munich

H01L 2100

438 7, 438 16, 438401

A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising: a) a center feature section that provides a critical dimension point along a given axis; b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; and c) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.

6472301, Oct 29, 2002

Oct 19, 1999

09/421161

Chuan Lin - Poughquag NY
Thomas Schafbauer - Wappingers Falls NY
Paul Wensley - Wappingers Falls NY

Infineon Technologies AG - Munich

H01L 218242

438524, 438433, 438527, 438224

A method (see e. g. , FIG. ) of fabricating a semiconductor device includes forming a trench in a semiconductor body. A dielectric layer is formed within the trench. Dielectric layer lines the sidewall and, possibly, the bottom portions of the trench in a manner where the thickness of the dielectric at the sidewall is greater than the thickness of the dielectric at the bottom. A dopant can then be implanted into the semiconductor body beneath the trench.

6566227, May 20, 2003

Aug 13, 2001

09/929334

Paul Wensley - Poughquag NY
Martin Commons - Stormville NY
Tobias Mono - Dresden, DE
Veit Klee - Pleasant Valley NY

Infineon Technologies AG - Munich

H01L 2176

438430, 438424, 438239, 438243, 438248

A method of providing shallow trench ( ) isolation for a semiconductor wafer ( ). Trenches ( ) are formed within a first semiconductor material ( ) and a pad nitride ( ), leaving a portion of first semiconductor material ( ) and pad nitride ( ) in a region between the trenches ( ). A second semiconductor material ( ) is deposited over the trenches ( ) to fill the trenches ( ) to a height below the first semiconductor material ( ) top surface. A first insulator ( ) is selectively formed over the second semiconductor material ( ). The pad nitride ( ) and a portion of the first semiconductor material ( ) between the trenches ( ) are removed to isolate element regions of the wafer ( ) and form straps ( ) having a low resistance.

6518151, Feb 11, 2003

Aug 7, 2001

09/924118

David Mark Dobuzinsky - New Windsor NY
Babar Ali Khan - Ossining NY
Joyce C. Liu - Hopewell Junction NY
Paul R. Wensley - Poughquag NY
Chienfan Yu - Highland Mills NY

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

H01L 2122

438551, 438258

A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

20040058550, Mar 25, 2004

Sep 19, 2002

10/247204

Tobias Mono - Dresden, DE
Veit Klee - Pleasant Valley NY, US
Paul Wensley - Poughquag NY, US
Martin Commons - Stormville NY, US

Infineon Technologies North America Corp.

H01L021/302
H01L021/461

438/708000

Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask separated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.