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Paul Allen Kayfes

from Beaverton, OR
Age ~63
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Also known as:
Paul A Kayfes, Paul Allen Kaymus
Phone and address:
16790 NW Sandelie Ct, Beaverton, OR 97006
Related to:
James T Kayfes, 63Molly A Kayfes, 32Lauren D Barnhart, 34John D Barnhart, 61Rosemari J Davis, 78Randall J Davis, 59Jason D Mims, 53Randall B Gregory, 70Rosemari Davis, 77Kimberly A Davis, 78Kristin A Kayfes, 59Johanna B Carlson, 82Kristin KayfesKimberly D Mims, 53Taylor E Kayfes, 33Brandon P Kayfes, 38Tracy A Gregory, 62
Connected to:
Marlane J Kayfes, 73Ryan T Kayfes, 37Janet L Kayfetz, 73Mark J Kayfez, 65Leyla Kayhan, 44Mehmet B Kayhan, 80Mona L Kayhan, 44Paul W Kayhart, 49Bahram K Kayhour, 73Abdullah Kayi, 45

Paul Kayfes Phones & Addresses

  • 16790 NW Sandelie Ct, Beaverton, OR 97006
  • 8684 Muledeer Dr, Beaverton, OR 97007
  • 390 Kotrik Pl, Beaverton, OR 97006
  • Hillsboro, OR
  • Portland, OR

Work

Company: Intel corporation Jan 1998 to Jan 2007 Position: Component design engineer

Education

School / High School: University of Portland 1981 to 1985

Skills

Microprocessors • Soc • Semiconductors • Ic • Pcie • Physical Design • Verilog • Vlsi • Fpga • Processors • Debugging • Asic • Integrated Circuit Design • Hardware Architecture

Industries

Computer Hardware

Resumes

Resumes

Paul Kayfes Photo 1

Engineering Design Manager At Intel

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Computer Hardware
Work:
Intel Corporation Jan 1998 - Jan 2007
Component Design Engineer
Intel Corporation Jan 1998 - Jan 2007
Engineering Design Manager at Intel
Pyramid Technology Jan 1990 - Jan 1998
Senior Hw Design Engineer
Biin 1989 - 1990
Hw Design Engineer
Floating Point Systems Jun 1985 - Jan 1988
Hw Design Engineer
Education:
University of Portland 1981 - 1985
Skills:
Microprocessors
Soc
Semiconductors
Ic
Pcie
Physical Design
Verilog
Vlsi
Fpga
Processors
Debugging
Asic
Integrated Circuit Design
Hardware Architecture

Publications

Us Patents

Error Reporting Network In Multiprocessor Computer

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US Patent:
7406632, Jul 29, 2008
Filed:
Jun 26, 2003
Appl. No.:
10/607517
Inventors:
Charles Sealey - Beaverton OR, US
John Lynch - Portland OR, US
Mark Myers - Portland OR, US
Jason Lewis - Keizer OR, US
Stacey Lloyd - Hillsboro OR, US
Paul Kayfes - Beaverton OR, US
Assignee:
Fujitsu Siemens Computers, LLC - Milpitas CA
International Classification:
G06F 11/00
US Classification:
714 48, 714 47
Abstract:
A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.

System And Method To Initialize Registers With An Eeprom Stored Boot Sequence

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US Patent:
20040215836, Oct 28, 2004
Filed:
Apr 22, 2003
Appl. No.:
10/421287
Inventors:
Wayne Moore - Hillsboro OR, US
Paul Kayfes - Beaverton OR, US
International Classification:
G06F003/00
US Classification:
710/001000
Abstract:
A system and method to initialize registers with an EEPROM stored boot sequence is described. The method includes reading configuration records from an EEPROM coupled to an ASIC upon system reset. The configuration records specify target configuration registers and data to be written to the registers. The configuration records are translated to register write requests and data is written to the target registers via a bus of the ASIC to initialize the registers. Other masters, such as a processor, may be blocked from accessing the registers during the initialization.
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Paul Allen Kayfes from Beaverton, OR, age ~63 Get Report