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Pantas Te Sutardja

from Saratoga, CA
Age ~61
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Also known as:
Pantas S Sutardja, Panpas Sutardja, Chi Wong Siu, Pantas A
Related to:
Hiu-Ming Wong, 51Ramah Sutardja, 60Anthony R Sutardja, 31Victor Sutardja, 29Sehat Sutardja, 63Wah S Wong, 75Chi Wong Siu, 91Agus Sutardja, 88Nicholas Sutardja, 34Lawrence Sutardja, 31Weili Dai, 63Diana J Carbone, 61Christoph Sutardja, 36
Connected to:
Amit H Sutaria, 47Arti M Sutaria, 52Deep P Sutaria, 35Dilip K Sutaria, 64Nupur D Sutaria, 34Rita J Sutaria, 58Surili D Sutaria, 41Ann M Sutay, 73Thomas Sutcavage, 57Aaron J Sutch, 36

Pantas Sutardja Phones & Addresses

  • Saratoga, CA
  • 18690 Blythswood Dr, Los Gatos, CA 95030
  • 781 Springwood Dr, San Jose, CA 95129 (408) 267-8519 (408) 446-3967
  • San Leandro, CA

Work

Company: Marvell semiconductor Jan 1995 to Feb 2014 Position: Chief technology officer

Education

Degree: Graduate or professional degree

Skills

Semiconductors • Asic • Soc • Ic • Debugging • Digital Signal Processors • System Architecture • Verilog • Firmware • Perl

Industries

Consumer Electronics

Resumes

Resumes

Pantas Sutardja Photo 1

Chief Executive Officer

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Location:
18690 Blythswood Dr, Los Gatos, CA 95030
Industry:
Consumer Electronics
Work:
Marvell Semiconductor Jan 1995 - Feb 2014
Chief Technology Officer
Latticework Jan 1995 - Feb 2014
Chief Executive Officer
Skills:
Semiconductors
Asic
Soc
Ic
Debugging
Digital Signal Processors
System Architecture
Verilog
Firmware
Perl

Business Records

Name / Title
Company / Classification
Phones & Addresses
Pantas Sutardja
Chief Technology Officer
Marvell Semiconductor, Inc
Mfg Electrical Measuring Instruments
5450 Bayfront Plz, Santa Clara, CA 95054
Pantas Sutardja
Chief Technology Officer
Marvell Technology Group Ltd
Holding Company · Offices of Other Holding Companies · Semiconductor and Related Device Manufacturing
5488 Marvell Ln, Santa Clara, CA 95054
700 1 Ave, Sunnyvale, CA 94089
(408) 222-2500, (408) 222-9233, (408) 222-8986, (408) 222-8921
Pantas D. Sutardja
Co-Founder
THE MARVELL CHARITABLE FUND, INC
Membership Organizations, Nec, Nsk
5488 Marvell Ln, Santa Clara, CA 95054
Pantas Sutardja
Chief Technology Officer
Syskonnect Inc
Whol Distributor & Service of Computer Interface Hardware & Software Equipment
5450 Bayfront Plz, Santa Clara, CA 95054
(408) 222-0809

Publications

Us Patents

High-Speed, Low Power, Medium Resolution Analog-To-Digital Converter And Method Of Stabilization

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US Patent:
RE37716, May 28, 2002
Filed:
Jan 17, 2001
Appl. No.:
09/760705
Inventors:
Sehat Sutardja - Cupertino CA
Pantas Sutardja - San Jose CA
Assignee:
Marvell International, Ltd. - Hamilton
International Classification:
H03M 110
US Classification:
341120, 341155, 341118, 341159, 341122
Abstract:
A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digital-to-analog converter are coupled to supply corrected reference voltages to each track/hold circuit. Outputs of the comparators are supplied to a decoder which produces the digital output representative of the input voltage. The converter is calibrated before it is used for conversion by sensing the input offset voltages of each of the comparators and by altering the reference voltage for each comparator to produce a calibrated reference voltage for each comparator. A digital representation of the calibrated reference voltage for each comparator is stored in a look-up table for retrieval as needed to supply to a particular track/hold circuit a corresponding calibrated analog reference voltage for a particular comparator. Digital representations in the look-up table may indicate switch settings required to provide corrected reference voltages, or may indicate the required corrected reference voltage that is supplied by digital to analog converter which converts the digital representation into an analog corrected reference voltage that is held by the track/hold circuit.

Controllable Integrator

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US Patent:
RE37739, Jun 11, 2002
Filed:
Jun 22, 2000
Appl. No.:
09/609007
Inventors:
Sehat Sutardja - Cupertino CA
Pantas Sutardja - San Jose CA
Assignee:
Marvell International Ltd.
International Classification:
G06G 764
US Classification:
327336, 327 91, 327 65
Abstract:
Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.

Apparatus And Method For Transient Suppression In Synchronous Data Detection Systems

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US Patent:
RE37751, Jun 18, 2002
Filed:
Oct 25, 2000
Appl. No.:
09/695035
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03K 1700
US Classification:
327100, 327155, 327559, 375345, 375376
Abstract:
Disclosed is a method for transient suppression in synchronous data protection systems which includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.

Digital Servo Channel For Recording Apparatus

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US Patent:
6430238, Aug 6, 2002
Filed:
Jun 27, 2000
Appl. No.:
09/605133
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvel International, Ltd. - Hamilton
International Classification:
H04L 2708
US Classification:
375345, 4552451, 369 4436
Abstract:
A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gain control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.

Digital Servo Demodulator With Synchronous Dithering And Method

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US Patent:
6507449, Jan 14, 2003
Filed:
Dec 9, 1998
Appl. No.:
09/208211
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvell International, Ltd. - Hamilton
International Classification:
G11B 5596
US Classification:
360 7702, 360 7717
Abstract:
The effective resolution of a Position Error Signal (PES) in a disk drive servo is increased by synchronously dithering the analog PES while sampling it with an Analog-to-Digital Converter (ADC). For each cycle of a burst field signal on a servo sector, a DC offset is added to the analog PES before sampling. The offset is changed periodically during the sampling of the burst field signal. The set of all DC offsets used is evenly spread over a range which is substantially equal to the size of the least significant bit of the ADC multiplied by a positive integer.

Acquistion Timing Loop For Read Channel

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US Patent:
6594098, Jul 15, 2003
Filed:
Sep 12, 2000
Appl. No.:
09/660392
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11B 509
US Classification:
360 65, 360 46
Abstract:
A signal from a storage medium is processed in a data channel to form digital data. An amplifier and a sampler convert the storage medium signal into a timed sample sequence. A first equalizer and adjuster operates to equalize the timed sample sequence and to adjust the gain of the amplifier and timing of the sampler in a preamble segment of the signal. A second equalizer and adjuster circuit to equalize the timed sample sequence for detection and to adjust the gain of the amplifier and the timing of the sampler operates in a user data segment of the signal. An FIR equalizing filter in the second equalizer and adjuster circuit is controlled by a set of parameters to accurately equalize a large range of waveforms in the user data segment of the signal and an FIR equalizing filter in the first equalizer and adjuster circuit is controlled by a smaller set of related set of parameters adapted to accommodate rapid adjustment during synchronization in the preamble segment of the signal.

Digital Servo Channel For Recording Apparatus

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US Patent:
6606358, Aug 12, 2003
Filed:
Apr 2, 2002
Appl. No.:
10/114578
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04L 2708
US Classification:
375345, 4552451, 369 4436
Abstract:
A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gear control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.

Gate Capacitor Stress Reduction In Cmos/Bicmos Circuit

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US Patent:
6633197, Oct 14, 2003
Filed:
Oct 27, 2000
Appl. No.:
09/697714
Inventors:
Pantas Sutardja - San Jose CA
Assignee:
Marvell International, Ltd. - Hamilton
International Classification:
H03K 17795
US Classification:
327530, 327538, 327534, 361111, 257532
Abstract:
Method and apparatus for using a MOSFET having a thin gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the MOSFET by applying a nonzero voltage to the source and the drain, and applying a voltage to a gate of the MOSFET. The voltage applied to the gate is greater than a voltage rating of the MOSFET but less than the sum of the voltage rating and the voltage applied to the source and the drain. The gate of the MOSFET may have a length that measures at least 150. 0 nanometers and no more than 350. 0 nanometers. The thin gate oxide layer may have a thickness that measures at least 2. 00 nanometers and no more than 7. 00 nanometers. The MOSFET may be constructed using CMOS technology or BiCMOS technology.
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Pantas Te Sutardja from Saratoga, CA, age ~61 Get Report