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Padmaraj Sanjeevarao

from Austin, TX
Age ~52
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Also known as:
Padmarat Sanjeevarao, Raj Sanjeev
Phone and address:
7121 Tanaqua Ln, Austin, TX 78739
Related to:
Deepa Sanjeevarao, 56
Connected to:
Prakash B Sanjeevaiah, 39Prashanth D Sanjeevi, 43Ruwan Sanjeewa, 47Singh G Sanjeet, 37Joan E Sanji, 86Houman Sanjideh, 70Erika Sanjines, 52Jorge M Sanjines, 75Maria I Sanjines, 64Rene W Sanjines, 71

Padmaraj Sanjeevarao Phones & Addresses

  • 7121 Tanaqua Ln, Austin, TX 78739
  • 16502 Goldenwood Way, Austin, TX 78737
  • 7631 Highway 290 W, Austin, TX 78736
  • 1063 Morse Ave, Sunnyvale, CA 94089
  • 730 Evelyn Ave, Sunnyvale, CA 94086
  • 1069 Greco Ave, Sunnyvale, CA 94087
  • Santa Clara, CA
  • San Diego, CA

Work

Company: Freescale semiconductor Sep 2005 Position: Non-volatile memory

Industries

Semiconductors

Resumes

Resumes

Padmaraj Sanjeevarao Photo 1

Non-Volatile Memory

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor
Non-Volatile Memory
Stmicroelectronics 1995 - 1998
Memory Design

Publications

Us Patents

Non-Volatile Memory Having A Static Verify-Read Output Data Path

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US Patent:
7692989, Apr 6, 2010
Filed:
Apr 26, 2007
Appl. No.:
11/740331
Inventors:
Padmaraj Sanjeevarao - Austin TX, US
David W. Chrudimsky - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/00
US Classification:
365205, 365191, 365201, 36518914, 36518915
Abstract:
A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

Memory With High Speed Sensing

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US Patent:
7701785, Apr 20, 2010
Filed:
Jun 23, 2008
Appl. No.:
12/144332
Inventors:
Padmaraj Sanjeevarao - Austin TX, US
Tahmina Akhter - Austin TX, US
David W. Chrudimsky - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/00
US Classification:
36518909, 365226
Abstract:
A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

Negative Voltage Generation

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US Patent:
7733126, Jun 8, 2010
Filed:
Mar 31, 2009
Appl. No.:
12/415159
Inventors:
Jon Choy - Austin TX, US
David W. Chrudimsky - Austin TX, US
Padmaraj Sanjeevarao - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03K 19/0175
US Classification:
326 68, 326 81
Abstract:
A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

Memory Device And Method Using Encode Values For Access Error Condition Detection

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US Patent:
8625365, Jan 7, 2014
Filed:
Aug 18, 2011
Appl. No.:
13/212478
Inventors:
Padmaraj Sanjeevarao - Austin TX, US
David W. Chrudimsky - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/00
US Classification:
36518907, 36523006
Abstract:
A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.

Scan Chain Verification Using Symbolic Simulation

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US Patent:
7055118, May 30, 2006
Filed:
Mar 1, 2004
Appl. No.:
10/790650
Inventors:
Harinath B. Kamepalli - Mountain View CA, US
Padmaraj Sanjeevarao - Sunnyvale CA, US
Chang-Jin Park - Cupertino CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 18
Abstract:
A method and apparatus for improved formal scan chain equivalence checking to verify the operation of components in a VLSI integrated circuit is described in connection with using symbolic simulation for verification of scan chain equivalency between different modeling representations of a circuit-under-test. The present invention enhances previous techniques by loading each scannable state-element in the circuit design with a symbolic expression that characterizes the logical location of the element and performing a scan shift operation to verify the contents of each scannable state-element at the scan-out and other primary output pins of the design.

Memory Read Circuitry With A Flipped Voltage Follower

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US Patent:
20220383925, Dec 1, 2022
Filed:
May 28, 2021
Appl. No.:
17/333109
Inventors:
- Austin TX, US
Jon Scott Choy - Austin TX, US
Padmaraj Sanjeevarao - Austin TX, US
International Classification:
G11C 11/16
Abstract:
A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Memory With One-Time Programmable (Otp) Cells

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US Patent:
20220301647, Sep 22, 2022
Filed:
Mar 18, 2021
Appl. No.:
17/249906
Inventors:
- Austin TX, US
Jacob T. Williams - Austin TX, US
Karthik Ramanan - Austin TX, US
Padmaraj Sanjeevarao - Austin TX, US
Maurits Mario Nicolaas Storms - Best, NL
International Classification:
G11C 17/18
G11C 17/16
G11C 11/16
Abstract:
A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Non-Volatile Memory (Nvm) With Word Line Driver/Decoder Using A Charge Pump Voltage

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US Patent:
20140269140, Sep 18, 2014
Filed:
Mar 14, 2013
Appl. No.:
13/826958
Inventors:
PADMARAJ SANJEEVARAO - Austin TX, US
DAVID W. CHRUDIMSKY - Austin TX, US
International Classification:
G11C 5/14
G11C 8/08
US Classification:
36523006
Abstract:
A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
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Padmaraj Sanjeevarao from Austin, TX, age ~52 Get Report