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Nicholas A Polomoff

from Hopewell Junction, NY
Age ~43
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Also known as:
Nick Alexander Polomoff, Nick A Polomoff
Connected to:
Francis A Polomsky, 95Jessica S Polomsky, 49Ronald J Polomski, 72Sara N Polomsky, 40Stacia A Polomsky, 55Brad M Polon, 61Isabel E Polon, 34James D Polon, 102John H Polon, 50Kelsey A Poloncic, 37

Nicholas Polomoff Phones & Addresses

  • Hopewell Junction, NY
  • 62 Rockview, Irvine, CA 92612 (203) 215-2990
  • Mohegan Lake, NY
  • White Plains, NY
  • West Hartford, CT
  • Milford, CT
  • Central, SC
  • Fishkill, NY
  • Clemson, SC

Work

Company: Material connexion Mar 2011 Position: Senior material scientist

Education

School / High School: University of Connecticut- Storrs, CT May 2011 Specialities: Ph.D. in Material Science and Engineering

Resumes

Resumes

Nicholas Polomoff Photo 1

Nicholas Polomoff White Plains, NY

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Work:
Material ConneXion

Mar 2011 to 2000
Senior Material Scientist
Lao Tzu

2008 to 2000
Graduate Student - NanoMeasurements Laboratory Manager
University of Connecticut

2005 to 2000
Graduate Student - Researcher
GE's Edgelab
Stamford, CT
Jan 2010 to May 2011
Research Analyst
Rhizome Integrated Corporation
New York, NY
2009 to 2010
Director of Research and Development
University of Connecticut
Storrs, CT
2006 to 2007
Teaching Assistant
University of Connecticut

2005 to 2006
Research Assistant - Research Staff Member and Applications Specialist
Dannalab

2005 to 2006
Research Assistant
Clemson University
Clemson, SC
2002 to 2004
Laboratory Assistant
Education:
University of Connecticut
Storrs, CT
May 2011
Ph.D. in Material Science and Engineering
University of Connecticut
Hartford, CT
May 2010
M.B.A. in Business Administration
University of Connecticut
Storrs, CT
May 2008
M.S. in Material Science and Engineering
Clemson University
Clemson, SC
May 2004
B.S. in Ceramic and Material Science and Engineering

Publications

Us Patents

Ic Structure With Interdigitated Conductive Elements Between Metal Guard Structures

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US Patent:
20200219826, Jul 9, 2020
Filed:
Jan 4, 2019
Appl. No.:
16/240436
Inventors:
- Grand Cayman, KY
Cathryn J. Christiansen - Richmond VT, US
Erdem Kaltalioglu - Newburgh NY, US
Ping-Chuan Wang - Hopewell Junction NY, US
Nicholas A. Polomoff - Irvine CA, US
International Classification:
H01L 23/00
G01N 27/12
H01L 23/538
Abstract:
An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

Interconnected Integrated Circuit (Ic) Chip Structure And Packaging And Method Of Forming Same

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US Patent:
20190287879, Sep 19, 2019
Filed:
Mar 15, 2018
Appl. No.:
15/921852
Inventors:
- Grand Cayman, KY
Mark W. Kuemerle - Essex Junction VT, US
Eric W. Tremble - Jericho VT, US
David B. Stone - Jericho VT, US
Nicholas A. Polomoff - Irvine CA, US
Eric S. Parent - Saratoga Springs NY, US
Jawahar P. Nayak - Clifton Park NY, US
Seungman Choi - Loudonville NY, US
International Classification:
H01L 23/488
H01L 25/065
Abstract:
An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Arc-Resistant Crackstop

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US Patent:
20190074253, Mar 7, 2019
Filed:
Sep 7, 2017
Appl. No.:
15/698027
Inventors:
- Grand Cayman, KY
Nicholas A. POLOMOFF - Irvine CA, US
Shaoning YAO - Chappaqua NY, US
Anupam ARORA - Burlington VT, US
International Classification:
H01L 23/00
H01L 23/62
H01L 23/66
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.

Crack Stop With Overlapping Vias

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US Patent:
20180315707, Nov 1, 2018
Filed:
Apr 26, 2017
Appl. No.:
15/498083
Inventors:
- Grand Cayman, KY
Kevin M. Boyd - Ballston Spa NY, US
Nicholas A. Polomoff - Irvine CA, US
Roderick A. Augur - Saratoga Springs NY, US
Jeannine M. Trewhella - Troy NY, US
International Classification:
H01L 23/528
H01L 23/522
H01L 23/00
Abstract:
A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

Maskless Selective Retention Of A Cap Upon A Conductor From A Nonconductive Capping Layer

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US Patent:
20180082965, Mar 22, 2018
Filed:
Nov 15, 2017
Appl. No.:
15/813342
Inventors:
- Armonk NY, US
Brittany L. Hedrick - Wappingers Falls NY, US
Nicholas A. Polomoff - White Plains NY, US
TaeHo Kim - Hwaseong, KR
Matthew E. Souter - Tustin CA, US
Assignee:
SUSS MicroTec Photonic Systems Inc. - Corona CA
International Classification:
H01L 23/00
Abstract:
A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

Maskless Selective Retention Of A Cap Upon A Conductor From A Nonconductive Capping Layer

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US Patent:
20180076160, Mar 15, 2018
Filed:
Nov 15, 2017
Appl. No.:
15/813311
Inventors:
- Armonk NY, US
Brittany L. Hedrick - Wappingers Falls NY, US
Nicholas A. Polomoff - White Plains NY, US
TaeHo Kim - Hwaseong, KR
Matthew E. Souter - Tustin CA, US
Assignee:
SUSS MicroTec Photonic Systems Inc. - Corona CA
International Classification:
H01L 23/00
Abstract:
A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

Maskless Selective Retention Of A Cap Upon A Conductor From A Nonconductive Capping Layer

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US Patent:
20170117241, Apr 27, 2017
Filed:
Oct 22, 2015
Appl. No.:
14/920197
Inventors:
- Armonk NY, US
Brittany L. Hedrick - Wappingers Falls NY, US
Nicholas A. Polomoff - White Plains NY, US
TaeHo Kim - Hwaseong, KR
Matthew E. Souter - Tustin CA, US
Assignee:
SUSS MicroTec Photonic Systems Inc. - Corona CA
International Classification:
H01L 23/00
Abstract:
A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

Flip Chip Alignment Mark Exposing Method Enabling Wafer Level Underfill

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US Patent:
20160365281, Dec 15, 2016
Filed:
Jun 11, 2015
Appl. No.:
14/736608
Inventors:
- Armonk NY, US
Kevin S. Petrarca - Newburgh NY, US
Nicholas A. Polomoff - White Plains NY, US
Katsuyuki Sakuma - Fishkill NY, US
International Classification:
H01L 21/78
H01L 21/56
Abstract:
Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.
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Nicholas A Polomoff from Hopewell Junction, NY, age ~43 Get Report