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Nicholas A Oleksinski

from Northville, MI
Age ~52
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Also known as:
Nicholas Alexander Oleksinski, Nick A Oleksinski, Nicholas A Oleksinksi, Nicholas A Olensinski, Oleksinski Oleksinski, Nicholas I
Phone and address:
638 Center St, Northville, MI 48167
(248) 596-1289
Related to:
Clifford J Miller, 76Max Miller, 47Margaret Burke, 50Raymond Miller, 56Charles Miller
Connected to:
Marilynn A Oleksinski, 71Thomas C Oleksinski, 86Chelsey E Oleksiuk, 31Irene S Oleksiuk, 85Nadiya Oleksiv, 34Peter J Oleksiw, 36Steven D Oleksiw, 64Sallie A Olekson, 67Agnieszka Oleksy, 39Peter F Oleksy, 105

Nicholas Oleksinski Phones & Addresses

  • 638 Center St, Northville, MI 48167 (248) 596-1289 (248) 735-0211
  • 42637 Northville Place Dr, Northville, MI 48167 (248) 374-8017 (248) 596-1289
  • 440 Newtonville Ave, Newtonville, MA 02460 (617) 630-1071
  • 8525 Honeytree Blvd, Canton, MI 48187
  • Wayne, MI
  • Jesse, WV
  • Cambridge, MA
  • Sudbury, MA

Work

Company: Lsi Position: Asic customer engineer

Education

Degree: BSE-EE School / High School: University of Michigan 1990 to 1994 Specialities: Control Systems, Digital Signal Processing

Skills

Asic • Physical Design • Static Timing Analysis • Soc • Timing Closure • Eda • Primetime • Vlsi • Cmos • Verilog • Floorplanning • Rtl Design • Dft • Ic • Tcl • Semiconductors • Perl • Integrated Circuits • Very Large Scale Integration • System on A Chip

Ranks

Certificate: Lynda.com, License C88Fd9

Industries

Semiconductors

Resumes

Resumes

Nicholas Oleksinski Photo 1

Senior Lead Engineer

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Location:
Detroit, MI
Industry:
Semiconductors
Work:
LSI
ASIC Customer Engineer
LSI Corporation since 1997
ASIC Customer Engineer
Education:
University of Michigan 1990 - 1994
BSE-EE, Control Systems, Digital Signal Processing
Skills:
Asic
Physical Design
Static Timing Analysis
Soc
Timing Closure
Eda
Primetime
Vlsi
Cmos
Verilog
Floorplanning
Rtl Design
Dft
Ic
Tcl
Semiconductors
Perl
Integrated Circuits
Very Large Scale Integration
System on A Chip
Certifications:
Lynda.com, License C88Fd9
License C88Fd9
Up and Running With C

Publications

Us Patents

Generic Methodology To Support Chip Level Integration Of Ip Core Instance Constraints In Integrated Circuits

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US Patent:
7669155, Feb 23, 2010
Filed:
Mar 26, 2007
Appl. No.:
11/728366
Inventors:
Balaji Ganesan - Fairview OR, US
David Vinke - Happy Valley OR, US
Ekambaram Balaji - Portland OR, US
Nicholas A. Oleksinski - Northville MI, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 1
Abstract:
A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Timing Constraint Generator

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US Patent:
20040268279, Dec 30, 2004
Filed:
Jun 24, 2003
Appl. No.:
10/602937
Inventors:
Nicholas Oleksinski - Northville MI, US
Michael Minter - Bowling Green KY, US
Assignee:
LSI LOGIC CORPORATION
International Classification:
G06F009/45
US Classification:
716/006000
Abstract:
A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.
Control profile
Nicholas A Oleksinski from Northville, MI, age ~52 Get Report