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Naveen Vittal Prabhu

from Folsom, CA
Age ~39
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Also known as:
Naveen Prabhu Vittal Prabhu, Naveen P Prabhu, Naveen Vittal, Naveen Prabhu U, Naveen U
Phone and address:
1384 Freswick Dr, Folsom, CA 95630
(682) 225-3665
Related to:
Christine E Biegert, 50
Connected to:
Alpana S Prabhu, 57Anupama Prabhu, 42Aruna V Prabhu, 74Ashish P Prabhu, 40Kamlesh Prabhu, 38Karan N Prabhu, 34Kishore S Prabhu, 48Nagabhushana Prabhu, 58Nalina Prabhu, 68Nitesh Prabhu, 34

Naveen Prabhu Phones & Addresses

  • 1384 Freswick Dr, Folsom, CA 95630 (682) 225-3665
  • Arlington, TX
  • Minneapolis, MN

Resumes

Resumes

Naveen Prabhu Photo 1

Logic Design Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Logic Design Engineer
Boston Scientific May 2008 - Aug 2008
Rf Test Engineer Intern
Education:
The University of Texas at Arlington 2006 - 2007
The University of Texas at Arlington;;2006 – 2007;
Skills:
Debugging
Verilog
Asic
Semiconductors
Vlsi
Testing
Perl
Systemverilog
Cadence Virtuoso
Embedded Systems
Eda
Naveen Prabhu Photo 2

Naveen Prabhu

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Naveen Prabhu Photo 3

Naveen Prabhu

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Location:
Sirsi Area, India
Industry:
Computer Software
Education:
SJCE , MYSORE
MCA

Publications

Us Patents

One Check Fail Byte (Cfbyte) Scheme

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US Patent:
20190355431, Nov 21, 2019
Filed:
Jun 3, 2019
Appl. No.:
16/430086
Inventors:
- Boise ID, US
Kristopher H. Gaewsky - El Dorado Hillis CA, US
Naveen Vittal Prabhu - Folsom CA, US
Purval S. Sule - Folsom CA, US
Trupti Bemalkhedkar - Folsom CA, US
Nehul N. Tailor - Phoenix AZ, US
Quan H. Ngo - Elk Grove CA, US
Dheeraj Srinivasan - San Jose CA, US
International Classification:
G11C 16/34
G11C 11/56
G11C 16/10
Abstract:
Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Solid State Drive With Reduced Host Oversight Of High Priority Read Command

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US Patent:
20190163403, May 30, 2019
Filed:
Jan 31, 2019
Appl. No.:
16/264390
Inventors:
- Santa Clara CA, US
Naveen Vittal PRABHU - Folsom CA, US
International Classification:
G06F 3/06
G06F 13/16
G06F 13/40
Abstract:
A method performed by a non volatile memory is described. The method includes receiving a first command from a controller to perform an operation. The method also includes receiving a second command from the controller to perform a read operation, where, the controller does not send a third command to suspend the operation between the first and second commands.

Method And Apparatus For Specifying Read Voltage Offsets For A Read Command

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US Patent:
20190102097, Apr 4, 2019
Filed:
Sep 29, 2017
Appl. No.:
15/721351
Inventors:
- Santa Clara CA, US
Xin Guo - San Jose CA, US
Naveen Vittal Prabhu - Folsom CA, US
Yu Du - Santa Clara CA, US
Purval Shyam Sule - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/06
Abstract:
In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

One Check Fail Byte (Cfbyte) Scheme

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US Patent:
20190096494, Mar 28, 2019
Filed:
Sep 27, 2017
Appl. No.:
15/717554
Inventors:
- Boise ID, US
Kristopher H. Gaewsky - El Dorado Hills CA, US
Naveen Vittal Prabhu - Folsom CA, US
Purval S. Sule - Folsom CA, US
Trupti Bemalkhedkar - Folsom CA, US
Nehul N. Tailor - Phoenix AZ, US
Quan H. Ngo - Elk Grove CA, US
Dheeraj Srinivasan - San Jose CA, US
International Classification:
G11C 16/34
G11C 16/10
Abstract:
Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

System And Method For Performing A Concurrent Multiple Page Read Of A Memory Array

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US Patent:
20190043564, Feb 7, 2019
Filed:
Dec 18, 2017
Appl. No.:
15/845500
Inventors:
- Santa Clara CA, US
BHARAT M. PATHAK - Folsom CA, US
BINH N. NGO - Folsom CA, US
NAVEEN VITTAL PRABHU - Folsom CA, US
KARTHIKEYAN RAMAMURTHI - Folsom CA, US
PRANAV KALAVADE - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/56
G11C 16/08
G11C 16/26
Abstract:
A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.
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Naveen Vittal Prabhu from Folsom, CA, age ~39 Get Report