Naved A Siddiqui

20210119021, Apr 22, 2021

Oct 22, 2020

17/077153

- Santa Clara CA, US
Matthias Bauer - Sunnyvale CA, US
Naved Ahmed Siddiqui - Sunnyvale CA, US
Phillip Stout - Santa Clara CA, US

Applied Materials, Inc. - Santa Clara CA

H01L 29/66
H01L 27/092
H01L 29/06
H01L 29/423
H01L 29/786
H01L 21/02
H01L 21/8238

Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

20210028067, Jan 28, 2021

Jul 22, 2019

16/517827

- Grand Cayman, KY
Naved A. Siddiqui - Sunnyvale CA, US
Shimpei Yamaguchi - Ibaraki, JP
Shreesh Narasimha - Clifton Park NY, US

H01L 21/8234
H01L 21/768
H01L 27/088
H01L 29/66
H01L 29/78

A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.

20200335591, Oct 22, 2020

Apr 17, 2019

16/386363

- Grand Cayman, KY
Daniel Jaeger - Saratoga Springs NY, US
Naved Siddiqui - Malta NY, US
Jessica Dechene - Watervliet NY, US
Daniel J. Dechene - Watervliet NY, US
Shreesh Narasimha - Charlotte NC, US

H01L 29/417
H01L 27/088
H01L 21/311
H01L 21/033
H01L 29/40

Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

20200211903, Jul 2, 2020

Jan 2, 2019

16/237757

- Grand Cayman, KY
JESSICA MARY DECHENE - Watervliet NY, US
HUI ZANG - Guilderland NY, US
NAVED AHMED SIDDIQUI - Latham NY, US

H01L 21/8234
H01L 27/088
H01L 29/66
H01L 21/308

The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.

20190295852, Sep 26, 2019

Mar 20, 2018

15/925928

- Grand Cayman, KY
Naved SIDDIQUI - Latham NY, US
Ankur ARYA - Saratoga Springs NY, US
John R. Sporre - Cohoes NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/311
H01L 29/66
H01L 21/768
H01L 21/3105
H01L 21/033
H01L 21/762

The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

20190027601, Jan 24, 2019

Jul 24, 2017

15/657373

- Grand Cayman, KY
Naved Siddiqui - Malta NY, US
Anthony I. Chou - Beacon NY, US

H01L 29/78
H01L 29/66

One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

20190019862, Jan 17, 2019

Jul 13, 2017

15/649294

- Grand Cayman, KY
Shahrukh Akbar KHAN - Danbury CT, US
Joseph SHEPARD, JR. - Poughkeepsie NY, US
Mohammad HASANUZZAMAN - Ballston Spa NY, US
Naved A. SIDDIQUI - Malta NY, US
Shafaat AHMED - Ballston Lake NY, US

H01L 29/06
H01L 29/423
H01L 29/78
H01L 29/66
H01L 21/306
H01L 21/3065
H01L 21/762
H01L 21/324

Methods for preventing fin bending in FinFET devices and related devices are provided. Embodiments include forming fins in a substrate; forming a non-conformal sacrificial layer over and between the fins to structurally conjoin the fins or an array of fins for structural integrity; forming a first gap-fill dielectric over the sacrificial layer and fins; recessing the first gap-fill dielectric to expose an upper portion of the fins and sacrificial layer; etching the sacrificial layer to expose the fins; forming a second gap-fill dielectric over the first gap-fill dielectric and over and between the fins; and recessing the second gap-fill dielectric to expose the upper portion of the fins.