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Nagesh K Vodrahalli

from Los Altos, CA
Age ~71
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Also known as:
Negesh Murthy, I Nagesh
Phone and address:
1081 Parma Way, Los Altos, CA 94024
(650) 490-0526
Related to:
Kailas N Vodrahalli, 26Kiran N Vodrahalli, 30Ingrid Vodrahalli, 64
Connected to:
Amy B Vodraska, 54Catherine S Vodrey, 62Francis H Vodusek, 50Barbara A Vodvarka, 73Frank E Vodvarka, 94James F Vodvarka, 90Arlene H Voecks, 87Karen L Voecks, 78Nicole M Voege, 49Jacob L Voegele, 40

Nagesh Vodrahalli Phones & Addresses

  • 1081 Parma Way, Los Altos, CA 94024 (650) 490-0526
  • Berkeley, CA
  • Phoenix, AZ
  • 20276 Pinntage Pkwy, Cupertino, CA 95014
  • Huntington, WV
  • Santa Clara, CA
  • Maricopa, AZ

Publications

Us Patents

Integrated Circuit Package Having A Substrate Vent Hole

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US Patent:
6490166, Dec 3, 2002
Filed:
Jun 11, 1999
Appl. No.:
09/330373
Inventors:
Suresh Ramalingam - Fremont CA
Nagesh Vodrahalli - Cupertino CA
Michael J. Costello - Phoenix AZ
Mun Leong Loke - Chandler AZ
Ravi V. Mahajan - Tempte AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2100
US Classification:
361760, 361764, 361820, 257778, 257737, 257738, 29841, 438 63, 438 64
Abstract:
The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

Electronic Assembly Comprising Solderable Thermal Interface

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US Patent:
6724078, Apr 20, 2004
Filed:
Aug 31, 2000
Appl. No.:
09/652430
Inventors:
Biswajit Sur - San Jose CA
Nagesh Vodrahalli - Phoenix AZ
Thomas Workman - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2312
US Classification:
257704, 257706, 257707, 257720, 257675, 257779, 257783, 438122, 438125, 438612, 438118
Abstract:
To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

Polarization-Insensitive Planar Lightwave Circuits And Method For Fabricating The Same

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US Patent:
6778750, Aug 17, 2004
Filed:
Jun 26, 2002
Appl. No.:
10/185219
Inventors:
Nagesh K. Vodrahalli - Cupertino CA
Achintya K. Bhowmik - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B 610
US Classification:
385130, 385 11, 385 14, 385 37
Abstract:
A planar lightwave circuit comprises a plurality of waveguides formed with a geometrical or refractive index properties that renders the planar lightwave circuit substantially polarization insensitive.

Compact Optical Package With Modular Optical Connector

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US Patent:
6860642, Mar 1, 2005
Filed:
Mar 14, 2002
Appl. No.:
10/099110
Inventors:
Nagesh K. Vodrahalli - Los Altos CA, US
Jaiom S. Sambyal - Cupertino CA, US
Biswajit Sur - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B006/36
G02B006/00
US Classification:
385 53, 385 89, 385134
Abstract:
An optical connector comprises an optical circuit and a package casing. The package casing has an integrated modular optical connector, which has multiple optical waveguides.

Crystal-Core Fiber Mode Converter For Low-Loss Polarization-Insensitive Planar Lightwave Circuits

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US Patent:
6879743, Apr 12, 2005
Filed:
Dec 19, 2001
Appl. No.:
10/028570
Inventors:
Achintya K. Bhowmik - San Jose CA, US
Nagesh K. Vodrahalli - Cupertino CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B006/12
US Classification:
385 14, 385 11, 385 34, 385 49, 385122, 385129, 385130, 385131, 385132
Abstract:
A planar lightwave circuit comprises a first portion of a waveguide, a second portion of a waveguide, and a segment of crystal core fiber coupling the first portion to the second portion of the waveguide. The crystal core fiber helps to reduce the polarization sensitivity of the waveguide. In one embodiment, multiple crystal core fibers are used in a planar lightwave circuit having multiple waveguides, such as an array waveguide grating.

Ultra-Thin Polarization Mode Converters Based On Liquid Crystal Materials

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US Patent:
6928200, Aug 9, 2005
Filed:
Oct 7, 2002
Appl. No.:
10/265873
Inventors:
Nagesh K. Vodrahalli - Cupertino CA, US
Achintya K. Bhowmik - San Jose CA, US
Connie C. Liu - San Jose CA, US
Takaharu Fujiyama - Los Gatos CA, US
Kenji Takahashi - San Jose CA, US
Biswajit Sur - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B006/00
US Classification:
385 11, 349194
Abstract:
A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.

High Performance Thermal Interface Curing Process For Organic Flip Chip Packages

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US Patent:
6982192, Jan 3, 2006
Filed:
Dec 30, 1999
Appl. No.:
09/475104
Inventors:
Nagesh Vodrahalli - Cupertino CA, US
Biswajit Sur - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01C 21/44
H05B 6/64
H05B 6/70
H05B 6/50
H01L 23/495
H01L 23/10
US Classification:
438122, 438106, 438112, 438118, 219678, 219690, 219759, 257675, 257706, 257719, 257796
Abstract:
An integrated circuit package which has a thermal epoxy that can be attached to an integrated circuit and a thermal element. The thermal epoxy can be cured with energy at a microwave frequency. Curing the thermal epoxy with microwave energy can minimize package warpage during the curing process.

Electronic Assembly Comprising Solderable Thermal Interface And Methods Of Manufacture

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US Patent:
7091063, Aug 15, 2006
Filed:
Feb 9, 2004
Appl. No.:
10/775890
Inventors:
Biswajit Sur - San Jose CA, US
Nagesh Vodrahalli - Phoenix AZ, US
Thomas Workman - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438118, 438106, 438119, 438121, 438122, 438612, 438613
Abstract:
To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.
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Nagesh K Vodrahalli from Los Altos, CA, age ~71 Get Report