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Anamul Hoque

from Chandler, AZ
Age ~53
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Also known as:
Muhammed A Hoque, Mdanamul D Hoque, Anumu Hoque, Md Hoque, Hoque Anamul, Hoque Md, L Hoque, Anamul D
Phone and address:
3953 E San Carlos Pl, Chandler, AZ 85249
(952) 953-9649
Related to:
Tasnim M Hossain, 52Suhel Ahmed, 50Reaj Ahmed, 37Patricia Coffey, 64Mahassen Hussein, 68
Connected to:
Ansarul Hoque, 71Ekramul Hoque, 42Fatimah Hoque, 36Mahbub U Hoque, 65Maher S Hoque, 43Mazedul Hoque, 47Moynul Hoque, 33Muhammed A Hoque, 64Natasha Hoque, 29Rafiqul Hoque, 52

Anamul Hoque Phones & Addresses

  • 3953 E San Carlos Pl, Chandler, AZ 85249 (952) 953-9649
  • Saint Paul, MN
  • Lakeville, MN
  • Orlando, FL
  • Plainsboro, NJ
  • Inver Grove Heights, MN
  • Dakota, MN
  • 2414 Ravens Crest Dr, Plainsboro, NJ 08536 (609) 799-9374

Emails

m***[email protected]

Resumes

Resumes

Anamul Hoque Photo 1

Senior Staff Analog Design Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation Sep 2014 - Oct 2018
Member of Technical Staff
Marvell Semiconductor Sep 2014 - Oct 2018
Senior Staff Analog Design Engineer
Lsi Corporation Mar 2004 - May 2014
Staff Analog Ic Design Engineer
Infineon Technologies Apr 2000 - Mar 2004
Rf Ic Design Engineer at Infineon Technology
Education:
Ucf College of Business 1998 - 2000
Masters, Electronics Engineering, Electronics Bangladesh University of Engineering and Technology 1989 - 1995
Bachelors, Electronics Engineering, Electronics
Skills:
Analog
Cmos
Mixed Signal
Analog Circuit Design
Ic
Semiconductors
Integrated Circuit Design
Asic
Cadence Virtuoso
Eda
Circuit Design
Debugging
Rf Design
Simulations
Integrated Circuits
Bicmos
Spectre
Low Power Design
Cadence Spectre
Anamul Hoque Photo 2

Anamul Hoque

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Anamul Hoque Photo 3

Anamul Hoque

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Anamul Hoque Photo 4

Anamul Hoque

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Anamul Hoque Photo 5

Anamul Hoque

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Anamul Hoque Photo 6

Anamul Hoque

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Anamul Hoque Photo 7

Anamul Hoque

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Anamul Hoque Photo 8

Sr. Design Engineer At Lsi

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Location:
Greater Minneapolis-St. Paul Area
Industry:
Semiconductors

Publications

Us Patents

Write Driver Monitoring And Detection

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US Patent:
7969677, Jun 28, 2011
Filed:
Mar 23, 2009
Appl. No.:
12/408847
Inventors:
Jeffrey A. Gleason - Burnsville MN, US
Anamul Hoque - Apple Valley MN, US
David W. Kelly - Eagan MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 27/36
G11B 5/02
US Classification:
360 31, 360 68
Abstract:
Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Tuning High-Side And Low-Side Cmos Data-Paths In Cml-To-Cmos Signal Converter

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US Patent:
20100244899, Sep 30, 2010
Filed:
Mar 30, 2009
Appl. No.:
12/413723
Inventors:
Anamul Hoque - Apple Valley MN, US
Cameron C. Rabe - Inver Grove Heights MN, US
International Classification:
H03K 19/0175
H03K 19/094
US Classification:
326 64, 326 63, 326115
Abstract:
Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity. Second circuitry is configured for adjusting, with respect to the first pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal.

Reference Voltage Circuit For Adaptive Power Supply

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US Patent:
20130201578, Aug 8, 2013
Filed:
Feb 7, 2012
Appl. No.:
13/367473
Inventors:
Anamul Hoque - Lakeville MN, US
Cameron C. Rabe - Inver Grove Heights MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 21/02
G05F 3/02
US Classification:
360 75, 327537, G9B 21003
Abstract:
Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Storage Device Having Degauss Circuitry With Separate Control Of Degauss Signal Steady State And Overshoot Portions

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US Patent:
20130271867, Oct 17, 2013
Filed:
Apr 16, 2012
Appl. No.:
13/447741
Inventors:
Boris Livshitz - Eagan MN, US
Anamul Hoque - Lakeville MN, US
Jason S. Goldberg - Saint Paul MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 20/10
US Classification:
360 75
Abstract:
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Storage Device Having Degauss Circuitry With Ramp Generator For Use In Generating Chirped Degauss Signal

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US Patent:
20140029138, Jan 30, 2014
Filed:
Jul 24, 2012
Appl. No.:
13/556480
Inventors:
Paul Mazur - Cottage Grove MN, US
Robert A. Norman - Bloomington MN, US
Jeffrey A. Gleason - Burnsville MN, US
Anamul Hoque - Lakeville MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 5/465
US Classification:
360111
Abstract:
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a chirped degauss signal to be applied to the write head by the write driver. The degauss circuitry comprises a ramp generator configured to generate a ramp signal for controlling a frequency of at least a portion of a waveform of the chirped degauss signal. The ramp signal generated by the ramp generator may comprise a current ramp that is applied to a control input of a current controlled oscillator of the degauss circuitry.

Storage Device Having Degauss Circuitry Generating Degauss Signal With Multiple Decay Segments

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US Patent:
20140071561, Mar 13, 2014
Filed:
Sep 7, 2012
Appl. No.:
13/606279
Inventors:
Boris Livshitz - Eagan MN, US
Paul Mazur - Cottage Grove MN, US
Anamul Hoque - Lakeville MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 5/465
US Classification:
360111
Abstract:
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a degauss signal to be applied to the write head by the write driver. The degauss signal has a waveform comprising a plurality of decay segments including at least one alternating current decay segment and at least one direct current decay segment. An initial decay segment of the plurality of decay segments may comprise an alternating current decay segment or a direct current decay segment, and may be immediately followed by a decay segment of the opposite type.

Self-Evaluating High Frequency, Bandwidth, And Dynamic Range Cellular Polar Transmit Signal Fidelity

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US Patent:
20210044459, Feb 11, 2021
Filed:
Mar 30, 2018
Appl. No.:
16/976537
Inventors:
- Cupertino CA, US
Anamul HOQUE - Chandler AZ, US
David NEWMAN - Tempe AZ, US
Stephen RECTOR - Tempe AZ, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H04L 25/02
H04B 17/24
H04L 27/36
H04B 17/00
Abstract:
A radio communication device includes a device substrate. A transmitter circuit is coupled to the device substrate to transmit a radio frequency signal to an antenna. The radio communication device also includes a receiver circuit coupled to the device substrate, where the receiver circuit includes an oscillator circuit to generate a baseband signal from a received radio frequency signal. The radio communication device further includes a feedback circuit coupled to the antenna and to the receiver circuit, where the feedback circuit couples a portion of the transmitted radio frequency signal to the oscillator circuit using a transmission line.

Process And Temperature Immunity In Circuit Design

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US Patent:
20200336144, Oct 22, 2020
Filed:
Mar 29, 2018
Appl. No.:
16/957615
Inventors:
- Santa Clara CA, US
Anamul Hoque - Chandler AZ, US
International Classification:
H03K 19/0185
G05F 3/24
H03F 1/02
H03F 1/30
H03F 3/195
H03F 3/24
H03F 3/30
Abstract:
An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).
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Anamul Hoque from Chandler, AZ, age ~53 Get Report