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Mihalis E Yannakakis

from New York, NY
Age ~68

Mihalis Yannakakis Phones & Addresses

  • 300 109Th St, Manhattan, NY 10025 (212) 665-7152
  • 460 Riverside Blvd, New York, NY 10027 (212) 665-7152
  • Highland Lakes, NJ
  • Bloomfield, NJ
  • 11 Lorraine Rd, Summit, NJ 07901 (908) 273-2860
  • Glencoe, IL
  • Palo Alto, CA
  • Princeton, NJ
  • Union, NJ

Publications

Us Patents

Model Checking Of Message Flow Diagrams

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US Patent:
6516306, Feb 4, 2003
Filed:
Aug 17, 1999
Appl. No.:
09/375657
Inventors:
Rajeev Alur - Ardmore PA
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06E 100
US Classification:
706 10, 703 2, 703 15
Abstract:
Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesirable executions of the model under analysis. From the model under analysis, linearizations are defined from the model and a finite test automaton is constructed from the linearizations. The test automaton and the specification automaton are combined and it is determined whether there is an execution in the intersection. Where no state in the specification automaton is reachable from the test automaton, the model is verified.

Directly Verifying A Black Box System

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US Patent:
6526544, Feb 25, 2003
Filed:
Sep 14, 1999
Appl. No.:
09/396830
Inventors:
Doron A. Peled - Gillette NJ
Moshe Y. Vardi - Bellaire TX
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 1750
US Classification:
716 4, 716 5
Abstract:
A system and method for direct black box system verification is provided. For any property, a sequence of inputs for the black box is determined that will verify that the system exhibits the property. Counterexamples of the property are detected without inferring the black boxs internal structure; that is, the verification proceeds without identifying all states and state transitions of the black box. A specification automaton operable to exhibit undesirable system behavior is constructed and it is then determined whether an accepting execution exists on the intersection of the black box and the specification automaton. To determine whether such an execution exists, the black box is configured such that it can be reset to its initial state upon command and such that the system indicates when an input is disabled from a current state. When an input is enabled, the implementation transitions to the next state. If an input is disabled, then there is no intersection on the input string.

Implied Message Sequence Charts

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US Patent:
6681264, Jan 20, 2004
Filed:
May 26, 2000
Appl. No.:
09/579188
Inventors:
Rajeev Alur - Ardmore PA
Kousha Etessami - New York NY
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 954
US Classification:
709318, 703 17, 706 10, 345440
Abstract:
A system and method for determining whether a set of message sequence charts (MSCs) is realizable or safely realizable in an implementation is provided. The determination is made by analyzing the set of MSCs for the existence of unspecified, implied MSCs. If the set of MSCs can be realized in a deadlock-free automaton, then the set of MSCs is safely realizable. If the set of MSCs is realizable (no implied MSCs exist), a state machine can be synthesized from the set of MSCs. If the set of MSCs is not realizable, then implied, unspecified (partial) MSCs are produced. Also, given an undesirable MSC, the system determines whether the set of required MSCs implies the given undesired MSC.

Automatic Generation And Regeneration Of A Covering Test Case Set From A Model

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US Patent:
6804634, Oct 12, 2004
Filed:
Feb 17, 2000
Appl. No.:
09/506297
Inventors:
Gerard J. Holzmann - Watchung NJ
Margaret H. Holzmann - Watchung NJ
James J. Striegel - Little Silver NJ
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 1750
US Classification:
703 2, 703 22, 714 25, 714 33, 714 37, 714 38
Abstract:
A method and apparatus for generating a covering set of test cases from a directed graph is provided. The directed graph includes nodes and edges connecting the nodes, and a test case is a path through the directed graph. To generate a partial set of test cases, a set of selected test cases is received. These test cases can be manually selected or they can be a maintained test case set. The edges or nodes on the directed graph (or requirements linked to nodes or edges) that are covered by the selected test cases are marked with an identifier. Test cases are then generated from the directed graph according to a coverage algorithm. Marked graph elements may, but need not, be included in the generated test cases. The resulting partial test case set together with the selected test cases satisfy the coverage criterion.

Timing Verification By Successive Approximation

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US Patent:
5483470, Jan 9, 1996
Filed:
Jun 29, 1992
Appl. No.:
7/906082
Inventors:
Rajeev Alur - Murray Hill NJ
Alon Itai - Westfield NJ
Robert P. Kurshan - New York NY
Mihalis Yannakakis - Summit NJ
Assignee:
AT&T Corp. - Murray Hill NJ
International Classification:
G06F 1700
US Classification:
364578
Abstract:
Apparatus for developing and verifying systems. The disclosed apparatus employs a computationally-tractable technique for verifying whether a system made up of a set of processes, each of which has at least one delay constraint associated with it, satisfies a given temporal property. The technique deals with the verification as a language inclusion problem, i. e. , it represents both the set of processes and the temporal property as automata and determines whether there is a restriction of the set of processes such that the language of the automaton representing the restricted set of processes is included in the language of the automaton representing the temporal property. The technique is computationally tractable because it deals with the problem iteratively: it tests whether a current restriction of the set of processes is included, and if not, it employs a counter-example for the inclusion to either determine that the delay constraints render satisfaction of the given temporal property or to derive a new restriction of the set of processes. Further included in the disclosure are techniques for checking the timing consistency of the counter-example with respect to a delay constraint and techniques for finding the optimal delay constraint.

Model Checking Of Hierarchical State Machines

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US Patent:
6324496, Nov 27, 2001
Filed:
Jun 18, 1998
Appl. No.:
9/099372
Inventors:
Rajeev Alur - Ardmore PA
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 1750
US Classification:
703 17
Abstract:
Model checking is applied to a hierarchical state machine (i. e. , a state machine having at least one state (i. e. , a superstate) that is itself a state machine) without first flattening the hierarchical state machine. In one embodiment, the model checking involves one or more or reachability, cycle-detection, linear-time requirements, and branching-time requirements analyses. For reachability analysis, in addition to keeping track of whether states have been visited, the algorithm also keeps track of the exit nodes for each superstate. Cycle-detection analysis has two phases: a primary phase in which target states are identified and a secondary phase in which it is determined whether identified target states are part of closed processing paths or loops. For cycle-detection analysis, the algorithm keeps track of (1) whether states have been visited during the primary phase, (2) the exit nodes for each superstate, and (3) whether states have been visited during the secondary phase. For linear-time requirements analysis, a formula is translated into an automaton, and a product construction is defined between the automaton and a hierarchical machine that yields a new hierarchical machine that is then analyzed using the cycle-detection algorithm.

Methods And Apparatus For Generating Passive Testers From Properties

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US Patent:
6061812, May 9, 2000
Filed:
Apr 3, 1998
Appl. No.:
9/054470
Inventors:
Gerard J. Holzmann - Murray Hill NJ
Mihalis Yannakakis - Summit NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
G06F 1100
US Classification:
714 38
Abstract:
Techniques and testers for testing a system U including the steps of (a) defining a formal specification of a logical property P that system U is required not to satisfy; (b) generating a passive testing module T based upon property P to monitor system U; (c) invoking a function F at specific invocation points during the execution of system U to compute an abstract representation of the state of system U at the current point of execution; (d) passing the abstract representation computed by function F to passive testing module T in order to determine whether the abstract representation of the execution of system U to the current point matches illegal property P; and (e) declaring a "fail" result if the abstract representation of the execution of system U to the current point matches illegal property P and declaring a "pass" result if the abstract representation of the execution of system U to the current point does not match illegal property P.

Wikipedia References

Mihalis Yannakakis Photo 1

Mihalis Yannakakis

About:
Born:

13 September 1953 • Athens , Greece

Work:
Area of science:

Computer scientist


Position:

Member of the United States National Academy of Engineering • Model

Education:
Studied at:

National Technical University of Athens


Area of science:

Computational complexity theory • Graph theory


Specialty:

Director


Academic degree:

Professor

Skills & Activities:
Ascribed status:

Fellow of the Association for Computing Machinery


Skill:

Algorithms • Progress • Computer science


Award:

Gold Award

Mihalis E Yannakakis from New York, NY, age ~68 Get Report