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Michael Batenburg Phones & Addresses

  • Oceanside, CA
  • Vista, CA

Publications

Us Patents

System And Method To Control A Power On Reset Signal

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US Patent:
20110241741, Oct 6, 2011
Filed:
Mar 31, 2010
Appl. No.:
12/752027
Inventors:
Steven M. Millendorf - San Diego CA, US
Michael K. Batenburg - San Diego CA, US
Sarath Chandra Kasarla - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/00
G06F 17/30
G06F 19/00
US Classification:
327143, 707756, 700121, 707E17044
Abstract:
A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.

Adaptive Access Control For Hardware Blocks

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US Patent:
20170249183, Aug 31, 2017
Filed:
May 15, 2017
Appl. No.:
15/595579
Inventors:
- San Diego CA, US
Osman KOYUNCU - San Diego CA, US
Michael BATENBURG - San Diego CA, US
International Classification:
G06F 9/455
G06F 9/50
G06F 21/82
G06F 13/40
Abstract:
System and method for providing adaptive access to a hardware block on a computer system. In one embodiment, a method includes receiving a first access request and a second access request with an access controller, wherein the second access request is received sequentially after the first access request, and the first access request includes a first master identification and the second access request includes a second master identification, determining if the second master identification is equal to the first master identification, providing access to the second access request if the second master identification is equal to the first master identification, wherein the first master identification is associated with one or more hardware block interface values, invalidating the one or more hardware block interface values associated with the first master identification if the second master identification is not equal to the first master identification, and associating the one or more hardware block interface values with the second master identification and a corresponding privilege.

Adaptive Access Control For Hardware Blocks

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US Patent:
20160259750, Sep 8, 2016
Filed:
Mar 4, 2015
Appl. No.:
14/638669
Inventors:
- San Diego CA, US
Osman KOYUNCU - San Diego CA, US
Michael BATENBURG - San Diego CA, US
International Classification:
G06F 13/40
G06F 9/455
Abstract:
System and method for providing adaptive access to a hardware block on a computer system. In one embodiment, a method includes receiving a first access request and a second access request with an access controller, wherein the second access request is received sequentially after the first access request, and the first access request includes a first master identification and the second access request includes a second master identification, determining if the second master identification is equal to the first master identification, providing access to the second access request if the second master identification is equal to the first master identification, wherein the first master identification is associated with one or more hardware block interface values, invalidating the one or more hardware block interface values associated with the first master identification if the second master identification is not equal to the first master identification, and associating the one or more hardware block interface values with the second master identification and a corresponding privilege.

Apparatus And Method To Set The Speed Of A Clock

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US Patent:
20150286242, Oct 8, 2015
Filed:
Apr 3, 2014
Appl. No.:
14/244626
Inventors:
- San Diego CA, US
Michael K. BATENBURG - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 1/08
Abstract:
Disclosed is an apparatus and method to set the speed of a clock. A computing device may include a processor and a scheduler of the processor, the scheduler may be configured to: receive a plurality of votes for requested bandwidths from a plurality of different execution environments; sum the requested bandwidths; and set the clock speed based upon the sum of the requested bandwidths.

Protection For System Configuration Information

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US Patent:
20140226426, Aug 14, 2014
Filed:
Feb 12, 2013
Appl. No.:
13/765559
Inventors:
- San Diego CA, US
Michael Batenburg - San Diego CA, US
Esin Terzioglu - San Diego CA, US
Yucong Tao - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 5/14
US Classification:
365226
Abstract:
Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Michael Batenburg from Oceanside, CADeceased Get Report