Mervyn Y Tan

7240306, Jul 3, 2007

Feb 24, 2005

10/906553

Robert J. Allen - Jericho VT, US
Peter K. Chan - Union City CA, US
Evanthia Papadopoulou - New York NY, US
Sarah C. Prue - Richmond VT, US
Mervyn Y. Tan - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G06F 19/00
G06F 17/10
G06F 11/00
G06K 9/03
G06K 9/52

716 4, 700110, 382149, 382154, 714 25

Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

7260790, Aug 21, 2007

Apr 27, 2004

10/709292

Robert J. Allen - Jericho VT, US
Michael S. Gray - Fairfax VT, US
Jason D. Hibbeler - Williston VT, US
Mervyn Yee-Min Tan - South Burlington VT, US
Robert F. Walker - St. George VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 2, 716 10

A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

7302653, Nov 27, 2007

Feb 24, 2005

10/906548

Robert J. Allen - Jericho VT, US
Mervyn Y. Tan - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 4

Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

7310788, Dec 18, 2007

Feb 24, 2005

10/906549

Robert J. Allen - Jericho VT, US
Mervyn Y. Tan - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G06F 17/10

716 4, 703 2

Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

7503020, Mar 10, 2009

Jun 19, 2006

11/424922

Robert J. Allen - Jericho VT, US
Faye D. Baker - Burlington VT, US
Albert M. Chu - Essex VT, US
Michael S. Gray - Fairfax VT, US
Jason Hibbeler - Williston VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Mervyn Y. Tan - Milton VT, US
Robert F. Walker - St. George VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 2, 716 5

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i. e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

7634745, Dec 15, 2009

Aug 2, 2006

11/461805

Robert J. Allen - Jericho VT, US
Sarah C. Braasch - Richmond VT, US
Mervyn Y. Tan - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 4, 716 5

In embodiments of a method critical area is calculated based on both independent and dependent compound fault mechanisms. Specifically, critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i. e. , top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.

7661080, Feb 9, 2010

Jan 24, 2007

11/626576

Evanthia Papadopoulou - Baldwin Place NY, US
Sarah Braasch - Richmond VT, US
Mervyn Y. Tan - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 4, 716 5

In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

7685553, Mar 23, 2010

Apr 11, 2007

11/733795

Evanthia Papadopoulou - Baldwin Place NY, US
Ruchir Puri - Baldwin Place NY, US
Mervyn Y. Tan - Hopewell Junction NY, US
Louise H. Trevillyan - Katonah NY, US
Hua Xiang - Ossining NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 13, 716 4, 716 7, 716 10, 716 12, 716 14, 703 1, 703 14

An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.