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Mervyn Tan Phones & Addresses

  • Santa Clara, CA
  • 88 Cobble Hill Rd, Milton, VT 05468
  • Sunnyvale, CA
  • Hopewell Junction, NY
  • Boulder Creek, CA
  • Nazareth, PA
  • South Burlington, VT
  • 2269 Fordham Dr, Santa Clara, CA 95051

Resumes

Resumes

Mervyn Tan Photo 1

Architechnologist

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Position:
Senior Software Engineer at Google
Location:
Santa Clara, California
Industry:
Computer Software
Work:
Google - Mountain View, CA since Nov 2007
Senior Software Engineer

IBM - Burlington, Vermont Area Sep 2000 - Oct 2007
Software Engineer

Wharton Business School - Greater Philadelphia Area Mar 1999 - Dec 1999
Software Programmer

Feith Systems & Software, Inc. Jun 1997 - Aug 1997
Software Engineer
Education:
Rensselaer Polytechnic Institute 2000 - 2004
MS, Computer Science
University of Pennsylvania 1996 - 2000
BS, Computer Science
University of Pennsylvania 1996 - 2000
BA, Physics
Skills:
C/C++ and Java programming languages
Web development
Functional, performance, and systems-integration test
GUI and HCI programming
Innovation. IP leadership and development
Object-oriented design and complexity management
Research and academic collaboration
Structured problem solving and mathematical skills
Project management and software development process
Mathematics
Cross-functional Team Leadership
Web Development
Testing
Integration
Java
Architecture
Unix
Software Project Management
Algorithms
Software Development
Software Engineering
Interests:
Photography, hiking, nature/outdoors, travel, video games, volleyball
Mervyn Tan Photo 2

Mervyn Tan

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Location:
Burlington, Vermont Area
Industry:
Semiconductors

Publications

Us Patents

Integrated Circuit Layout Critical Area Determination Using Voronoi Diagrams And Shape Biasing

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US Patent:
7240306, Jul 3, 2007
Filed:
Feb 24, 2005
Appl. No.:
10/906553
Inventors:
Robert J. Allen - Jericho VT,
Peter K. Chan - Union City CA,
Evanthia Papadopoulou - New York NY,
Sarah C. Prue - Richmond VT,
Mervyn Y. Tan - South Burlington VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 19/00
G06F 17/10
G06F 11/00
G06K 9/03
G06K 9/52
US Classification:
716 4, 700110, 382149, 382154, 714 25
Abstract:
Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

Integrated Circuit Yield Enhancement Using Voronoi Diagrams

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US Patent:
7260790, Aug 21, 2007
Filed:
Apr 27, 2004
Appl. No.:
10/709292
Inventors:
Robert J. Allen - Jericho VT,
Michael S. Gray - Fairfax VT,
Jason D. Hibbeler - Williston VT,
Mervyn Yee-Min Tan - South Burlington VT,
Robert F. Walker - St. George VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2, 716 10
Abstract:
A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

Probability Of Fault Function Determination Using Critical Defect Size Map

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US Patent:
7302653, Nov 27, 2007
Filed:
Feb 24, 2005
Appl. No.:
10/906548
Inventors:
Robert J. Allen - Jericho VT,
Mervyn Y. Tan - South Burlington VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4
Abstract:
Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

Sample Probability Of Fault Function Determination Using Critical Defect Size Map

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US Patent:
7310788, Dec 18, 2007
Filed:
Feb 24, 2005
Appl. No.:
10/906549
Inventors:
Robert J. Allen - Jericho VT,
Mervyn Y. Tan - South Burlington VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 17/10
US Classification:
716 4, 703 2
Abstract:
Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

Ic Layout Optimization To Improve Yield

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US Patent:
7503020, Mar 10, 2009
Filed:
Jun 19, 2006
Appl. No.:
11/424922
Inventors:
Robert J. Allen - Jericho VT,
Faye D. Baker - Burlington VT,
Albert M. Chu - Essex VT,
Michael S. Gray - Fairfax VT,
Jason Hibbeler - Williston VT,
Daniel N. Maynard - Craftsbury Common VT,
Mervyn Y. Tan - Milton VT,
Robert F. Walker - St. George VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2, 716 5
Abstract:
A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i. e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Method For Computing The Critical Area Of Compound Fault Mechanisms

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US Patent:
7634745, Dec 15, 2009
Filed:
Aug 2, 2006
Appl. No.:
11/461805
Inventors:
Robert J. Allen - Jericho VT,
Sarah C. Braasch - Richmond VT,
Mervyn Y. Tan - South Burlington VT,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 5
Abstract:
In embodiments of a method critical area is calculated based on both independent and dependent compound fault mechanisms. Specifically, critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i. e. , top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.

Method And Apparatus For Net-Aware Critical Area Extraction

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US Patent:
7661080, Feb 9, 2010
Filed:
Jan 24, 2007
Appl. No.:
11/626576
Inventors:
Evanthia Papadopoulou - Baldwin Place NY,
Sarah Braasch - Richmond VT,
Mervyn Y. Tan - Hopewell Junction NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 5
Abstract:
In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

System And Method For Global Circuit Routing Incorporating Estimation Of Critical Area Estimate Metrics

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US Patent:
7685553, Mar 23, 2010
Filed:
Apr 11, 2007
Appl. No.:
11/733795
Inventors:
Evanthia Papadopoulou - Baldwin Place NY,
Ruchir Puri - Baldwin Place NY,
Mervyn Y. Tan - Hopewell Junction NY,
Louise H. Trevillyan - Katonah NY,
Hua Xiang - Ossining NY,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 13, 716 4, 716 7, 716 10, 716 12, 716 14, 703 1, 703 14
Abstract:
An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
Mervyn Y Tan from Santa Clara, CA, age ~43 Get Report