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Matthew George Dayley

from Wellsville, UT
Age ~47
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Also known as:
Matthew G Dayley, Matthew A Dayley, Matthew J Dayley, Matt Dayley, Mathew G Dayley, Marcus Dayley, Maria Dayley, Michael Dayley, Matt Dailey, Matt Daly
Connected to:
Alicia V Dayley, 42Bob R Dayley, 91Brent A Dayley, 55Jack L Dayley, 95Josh L Dayley, 38Lisa Dayley, 54Nedda J Dayley, 45Marina Y Daylis, 47Kyle A Daylong, 65Andrew P Daylor, 55

Matthew Dayley Phones & Addresses

  • Wellsville, UT
  • Brigham City, UT
  • Plymouth, CA
  • Cameron Park, CA
  • 684 Excelsior Rd, Placerville, CA 95667
  • Cumming, GA
  • Hillsboro, OR
  • Tempe, AZ
  • Mesa, AZ

Publications

Us Patents

Low Current Consumption Detector Circuit And Applications

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US Patent:
7230456, Jun 12, 2007
Filed:
Feb 24, 2004
Appl. No.:
10/786517
Inventors:
Matthew G. Dayley - Placerville CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/153
US Classification:
327 50, 327 78, 327143, 361 58
Abstract:
A low current consumption detector circuit, and its applications are described herein.

Multi-Stage Digital-To-Analog Converter

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US Patent:
7265698, Sep 4, 2007
Filed:
Jan 17, 2006
Appl. No.:
11/333913
Inventors:
Richard E. Fackenthal - Folsom CA, US
Matthew G. Dayley - Placerville CA, US
Saad P. Monasa - Sacramento CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03M 1/66
US Classification:
341145, 341144, 341156
Abstract:
A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Multi-Stage Digital-To-Analog Converter

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US Patent:
7034732, Apr 25, 2006
Filed:
Dec 30, 2004
Appl. No.:
11/026906
Inventors:
Richard E. Fackenthal - Folsom CA, US
Matthew G. Dayley - Placerville CA, US
Saad P. Monasa - Sacramento CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03M 1/66
US Classification:
341146, 341144
Abstract:
A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Voltage Regulator

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US Patent:
20190006993, Jan 3, 2019
Filed:
Jun 30, 2017
Appl. No.:
15/640218
Inventors:
- Santa Clara CA, US
Liyao Miao - Cupertino CA, US
Matthew G. Dayley - Plymouth CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03F 1/02
H02M 3/04
Abstract:
Technology for a system operable to regulate an output voltage is described. The system can include an active amplifier configured to amplify an input voltage to produce the output voltage when there is active current consumption at the output voltage of the system. The system can include a standby amplifier configured to switch between amplifying the input voltage for a defined period of time and not amplifying the input voltage for a defined period of time to maintain a desired value for the output voltage of the system.

Low-Power, High-Accuracy Current Reference For Highly Distributed Current References For Cross Point Memory

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US Patent:
20140293714, Oct 2, 2014
Filed:
Mar 29, 2013
Appl. No.:
13/853813
Inventors:
Matthew G. Dayley - Plymouth CA, US
Yadhu Vamshi S. Vancha - Rancho Cordova CA, US
International Classification:
G11C 5/14
G05F 3/08
US Classification:
36518909, 323314
Abstract:
A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.
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Matthew George Dayley from Wellsville, UT, age ~47 Get Report