US Patent:
20120286818, Nov 15, 2012
Inventors:
Himaja H. Bhatt - Cardiff by the Sea CA, US
Martin E. Parley - Carlsbad CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G01R 31/00
Abstract:
Systems, methods, devices, and computer program products are described for allowing optical backside failure analysis of a wire-bonded semiconductor device concurrent with electrical testing of the device. For example, a semiconductor device is prepared and mounted in the optical testing subsystem, such that a circuit region of the device is exposed to an optical testing environment, and an analog to the original array of the device is presented via the optical testing subsystem as a derived array. The electrical testing subsystem converts the derived array to a test array, and presents the test array in a way that is physically and electrically compatible with a test socket of an electrical testing environment. By coupling the electrical testing subsystem with the optical testing subsystem, a pin-to-pin coupling may be effectuated between the test array of the test socket and bonding locations on the device corresponding to the device's original array.