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Marc E Sawyer

from Horse Shoe, NC
Age ~65

Marc Sawyer Phones & Addresses

  • 1705 Brickyard Rd, Horse Shoe, NC 28742 (828) 545-3440
  • Hendersonville, NC
  • Asheville, NC
  • Orlando, FL
  • 1040 Stratford Pl, Melbourne, FL 32940 (321) 259-6108
  • 553 Carmel Rd, Melbourne, FL 32940 (321) 259-6108
  • Palm Bay, FL
  • Palm Coast, FL
  • 1040 Stratford Pl, Melbourne, FL 32940 (239) 821-7522

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

Professional Records

Lawyers & Attorneys

Marc Sawyer Photo 1

Marc Sawyer - Lawyer

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ISLN:
923451492
Admitted:
2011

Resumes

Resumes

Marc Sawyer Photo 2

Marc Sawyer

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Location:
Austin, Texas
Industry:
Publishing
Marc Sawyer Photo 3

Marc Sawyer

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Marc S. Sawyer
SENIOR RESOURCE AGENCY, INC

Publications

Us Patents

Clock Extractor For High Speed, Variable Data Rate Communication System

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US Patent:
59636084, Oct 5, 1999
Filed:
Jun 26, 1997
Appl. No.:
8/882923
Inventors:
Paul W. Casper - West Melbourne FL
Marc E. Sawyer - Melbourne FL
Assignee:
Broadband Communications Products, Inc. - Melbourne FL
International Classification:
H03D 324
US Classification:
375373
Abstract:
To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.

Gigabit Data Rate Extended Range Fiber Optic Communication System And Transponder Therefor

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US Patent:
60756349, Jun 13, 2000
Filed:
Aug 5, 1998
Appl. No.:
9/129664
Inventors:
Paul W. Casper - Melbourne FL
James W. Toy - Melbourne FL
Marc Sawyer - Melbourne FL
Assignee:
JDS Uniphase Corporation, UBP - Melbourne FL
International Classification:
H04B 1000
US Classification:
359152
Abstract:
A fiber optic digital communication system and associated transponder architecture interfaces Gigabit Ethernet digital data over an extended range fiber optic link (e. g. upwards of 30 to 100 km), using digital data signal regeneration and optical signal processing components, that pre- and post-compensate for distortion and timing jitter, and thereby ensure accurate regeneration of the data at the far end of the extended distance fiber optic link. Regeneration in both the transmit and receive paths compensates for signal degradation resulting from the very substantial `long haul` fiber distance between transponder sites, and timing jitter customarily present in low cost short haul fiber optic transceiver components. A high speed, low jitter, limiting current driver drives a distributed feedback laser, minimizing jitter generation, and optimizing range extension margin.

Method And Apparatus For Extracting An Embedded Clock From A Digital Data Signal

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US Patent:
58387498, Nov 17, 1998
Filed:
Jun 5, 1995
Appl. No.:
8/462168
Inventors:
Paul W. Casper - West Melbourne FL
Jeffrey S. Grant - Palm Bay FL
Marc E. Sawyer - Melbourne FL
Assignee:
Broadband Communications Products, Inc. - West Melbourne FL
International Classification:
H04L 700
US Classification:
375376
Abstract:
A data and clock recovery arrangement, for a high speed fiber optic digital communication system in which a serial digital bit stream is pre-scramble encoded by interleaving complementary pairs of overhead bits between successive groups of data bits, and then scrambled and transmitted to a receive site, comprises a data rate independent variable bit rate synchronizer, a descrambler and a decoder. The data rate independent variable bit synchronizer processes the received scrambled and encoded digital bit stream to derive a variable data rate synchronization clock signal. The synchronizer is capable of accepting any data rate within the operational data clock signal range of the system, and automatically tunes itself to the data clock signal embedded in the received scrambled and encoded serial data stream, so as to output respective scrambled and encoded serial data and clock signals. The descrambler descrambles the scrambled and encoded serial digital bit stream using the variable data rate synchronization clock signal, and the decoder decodes the descrambled serial digital bit stream to extract groups of data bits exclusive of the complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of the data bits.
Marc E Sawyer from Horse Shoe, NC, age ~65 Get Report