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Lukito Muliadi

from San Jose, CA
Age ~47
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Also known as:
Muliadi Lukito, Lukito I
Phone and address:
2804 Hemlock Ave, San Jose, CA 95128
Related to:
Jon Muliadi, 52Kathy JiangEdhi S MuliadiRong J Muliadi, 48Kathy MuliadiYiqun Jiang
Connected to:
Mark D Mulias, 71Katherine M Mulica, 59Matthew W Mulica, 44Thomas Mulica, 81Walter S Mulica, 75Angela R Mulichak, 53Bryan P Mulick, 57Jeff J Mulick, 53Robert F Mulick, 89Ryan J Mulick, 37

Lukito Muliadi Phones & Addresses

  • 2804 Hemlock Ave, San Jose, CA 95128
  • 2934 Vivian Ln, San Jose, CA 95124
  • 3190 Bascom Ave, San Jose, CA 95124
  • Cupertino, CA
  • Fort Worth, TX
  • 127 Ashbrook Trl, Forney, TX 75126
  • Los Altos, CA
  • Richmond, CA
  • 3108 White Ct, San Jose, CA 95127

Work

Company: Ambarella Aug 2010 Position: Design manager

Education

Degree: Master of Science School / High School: University of California, Berkeley 1997 to 1999 Specialities: Electrical Engineering

Skills

Logic Design • Asic

Languages

English

Industries

Consumer Electronics

Resumes

Resumes

Lukito Muliadi Photo 1

Senior Design Manager

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Location:
20488 Stevens Creek Blvd, Cupertino, CA 95014
Industry:
Consumer Electronics
Work:
Ambarella since Aug 2010
Design Manager
NVIDIA Jun 1999 - Aug 2010
Hardware Engineering Manager
Education:
University of California, Berkeley 1997 - 1999
Master of Science, Electrical Engineering Purdue University 1995 - 1997
Bachelor of Science, Electrical Engineering
Skills:
Logic Design
Asic
Languages:
English

Publications

Us Patents

Apparatus And Method For Performing Blit Operations Across Parallel Processors

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US Patent:
8059128, Nov 15, 2011
Filed:
Apr 19, 2006
Appl. No.:
11/407464
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US
Lukito Muliadi - San Jose CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 15/80
G06F 21/00
US Classification:
345505, 345530, 345543, 711168
Abstract:
A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.

Data Packer For Packing And Aligning Write Data

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US Patent:
8135885, Mar 13, 2012
Filed:
Oct 30, 2008
Appl. No.:
12/262138
Inventors:
Raymond Hoi Man Wong - Santa Clara CA, US
Samuel Hammond Duncan - Arlington MA, US
Lukito Muliadi - San Jose CA, US
Madhukiran V. Swarna - Portland OR, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/00
G06F 3/00
US Classification:
710 52, 710 8, 710 15
Abstract:
A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Bandwidth Impedance Matching And Starvation Avoidance By Read Completion Buffer Allocation

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US Patent:
8279231, Oct 2, 2012
Filed:
Oct 29, 2008
Appl. No.:
12/260985
Inventors:
Samuel Hammond Duncan - Arlington MA, US
John H. Edmondson - Arlington MA, US
Raymond Hoi Man Wong - Santa Clara CA, US
Lukito Muliadi - San Jose CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/02
US Classification:
345543, 711E12002
Abstract:
Read completion buffer space is allocated in accordance with a preset limit. When a read request is received from a client, the sum of a current allocation of the read completion buffer space and a new allocation of the read completion buffer space required by the read request is compared with the preset limit. If the preset limit is not exceeded, read completion buffer space is allocated to the read request. If the preset limit is exceeded, the read request is suspended until sufficient data is read out from the read completion buffer.

Data Packer For Packing And Aligning Write Data

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US Patent:
8380895, Feb 19, 2013
Filed:
Feb 15, 2012
Appl. No.:
13/397583
Inventors:
Raymond Hoi Man Wong - Santa Clara CA, US
Samuel Hammond Duncan - Arlington MA, US
Lukito Muliadi - San Jose CA, US
Madhukiran V. Swarna - Portland OR, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 52, 710 2, 710 5, 710 8, 710 36
Abstract:
A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Data Packer For Packing And Aligning Write Data

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US Patent:
8380896, Feb 19, 2013
Filed:
Feb 15, 2012
Appl. No.:
13/397586
Inventors:
Raymond Hoi Man Wong - Santa Clara CA, US
Samuel Hammond Duncan - Arlington MA, US
Lukito Muliadi - San Jose CA, US
Madhukiran V. Swarna - Portland OR, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 52, 710 2, 710 5, 710 8, 710 36
Abstract:
A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Data Packer For Packing And Aligning Write Data

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US Patent:
8396993, Mar 12, 2013
Filed:
Feb 15, 2012
Appl. No.:
13/397591
Inventors:
Raymond Hoi Man Wong - Santa Clara CA, US
Samuel Hammond Duncan - Arlington MA, US
Lukito Muliadi - San Jose CA, US
Madhukiran V. Swarna - Portland OR, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 5, 710 2, 710 8, 710 36, 710 52
Abstract:
A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Apparatus And Method For Selective Attribute Distribution To Parallel Processors

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US Patent:
7522169, Apr 21, 2009
Filed:
Dec 13, 2005
Appl. No.:
11/300228
Inventors:
Lukito Muliadi - San Jose CA, US
Justin S. Legakis - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 1/20
G06F 15/16
G06F 15/80
G06F 9/46
US Classification:
345506, 345502, 345503, 345505, 345520, 345522, 718105
Abstract:
A graphics processing unit has a set of parallel processing units. A primitive pipeline delivers tiles of a primitive to selected processing units of the set of processing units. An attribute pipeline distributes attributes to the selected processing units when the end of the primitive is reached, while withholding attributes from the remaining processing units of the set of processing units.
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Lukito Muliadi from San Jose, CA, age ~47 Get Report