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Loren A Chow

from Los Altos, CA
Age ~55
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Also known as:
Loren Anton Chow, Loren Te Chow, Loren A Lochow, Lorena Chow, Loren Ko
Phone and address:
891 Nancy Ln, Los Altos, CA 94024
Related to:
Michelle M Koo, 28Hannah KooDong Koo, 31Minjoo KooHee K Young
Connected to:
Adrian J Chow, 44Alroy A Chow, 87Amber L Chow, 39Andre Y Chow, 76Aries H Chow, 50Arlene B Chow, 65Belinda C Chow, 41Benjamin B Chow, 51Bradford M Chow, 72Candy Chow, 42

Loren Chow Phones & Addresses

  • 891 Nancy Ln, Los Altos, CA 94024
  • Santa Clara, CA
  • 2317 Byrnes Rd, Hopkins, MN 55305 (952) 544-8071
  • Minnetonka, MN
  • Los Angeles, CA
  • Mountain View, CA

Publications

Us Patents

Composite Dielectric Layers

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US Patent:
6674146, Jan 6, 2004
Filed:
Aug 8, 2002
Appl. No.:
10/215130
Inventors:
Loren A. Chow - Santa Clara CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2900
US Classification:
257508, 257506, 257501, 257 41, 438348, 438361, 438207, 438427
Abstract:
An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated from the contact point by the first dielectric layer. Collectively, the first and second dielectric layers comprise a composite dielectric layer having a composite dielectric constant value. The contribution of the first dielectric layer to the composite dielectric value is up to 20 percent. Also, a method including depositing a composite dielectric layer over a contact point on a substrate, the composite dielectric layer comprising a first material having a dielectric constant less than 5 and a second different second material, and forming a conductive interconnection through the composite dielectric layer to the contact point.

Composite Dielectric Layers

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US Patent:
6876081, Apr 5, 2005
Filed:
Sep 8, 2003
Appl. No.:
10/659068
Inventors:
Loren A. Chow - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L023/48
US Classification:
257758, 257210, 257211, 257759, 257760
Abstract:
An apparatus including a contact point formed on a device layer of a circuit substrate or interconnect layer on a substrate; a first dielectric layer including cubic boron nitride on the substrate; and a different second dielectric layer on the substrate and separated from the device layer by the first dielectric layer. Also, an apparatus including a circuit substrate including a device layer and a composite dielectric layer. The composite dielectric includes a first dielectric material including cubic boron nitride and a different second dielectric material. The first dielectric material surrounds the second dielectric material.

Iii-V And Ii-Vi Compounds As Template Materials For Growing Germanium Containing Film On Silicon

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US Patent:
7202503, Apr 10, 2007
Filed:
Jun 30, 2004
Appl. No.:
10/883295
Inventors:
Loren Chow - Santa Clara CA, US
Mohamad Shaheen - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/22
H01L 29/06
H01L 31/0328
US Classification:
257 78, 257 19, 257 20, 257190, 257191, 257192, 257614, 257616, 438933
Abstract:
An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III–V elements and a combination of II–VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

Buffer Layers For Device Isolation Of Devices Grown On Silicon

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US Patent:
7494911, Feb 24, 2009
Filed:
Sep 27, 2006
Appl. No.:
11/527785
Inventors:
Mantu K. Hudait - Portland OR, US
Mohamad A. Shaheen - Portland OR, US
Loren A. Chow - Santa Clara CA, US
Peter G. Tolchinsky - Beaverton OR, US
Joel M. Fastenau - Bethlehem PA, US
Dmitri Loubychev - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/28
H01L 21/20
H01L 21/00
US Classification:
438604, 438483, 438 46, 438 29, 257E21218
Abstract:
Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Dislocation-Free Insb Quantum Well Structure On Si Using Novel Buffer Architecture

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US Patent:
7573059, Aug 11, 2009
Filed:
Aug 2, 2006
Appl. No.:
11/501253
Inventors:
Mantu K. Hudait - Portland OR, US
Mohamad A. Shaheen - Portland OR, US
Loren A. Chow - Santa Clara CA, US
Peter G. Tolchinsky - Beaverton OR, US
Dmitri Loubychev - Bethlehem PA, US
Joel M. Fastenau - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/06
US Classification:
257 14, 257E29068, 257E29081, 257E29091
Abstract:
A device grade III-V quantum well structure formed on a silicon substrate using a composite buffer architecture and the method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×10cmto be formed on silicon substrates. In an embodiment of the present invention, an InSb quantum well layer is sandwiched between two larger band gap barrier layers. In an embodiment of the present invention, InSb quantum well layer is strained. In a specific embodiment, the two larger band gap barrier layers are graded.

Methods Of Forming Buffer Layer Architecture On Silicon And Structures Formed Thereby

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US Patent:
7687799, Mar 30, 2010
Filed:
Jun 19, 2008
Appl. No.:
12/214737
Inventors:
Mantu K. Hudait - Portland OR, US
Peter G. Tolchinsky - Beaverton OR, US
Loren A. Chow - Santa Clara CA, US
Dmitri Loubychev - Bethlehem PA, US
Joel M. Fastenau - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 31/00
H01L 21/338
US Classification:
257 14, 257194, 438172, 438478
Abstract:
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an InAlAs bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InAlAs layer on the InAlAs bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.

Buffer Layers For Device Isolation Of Devices Grown On Silicon

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US Patent:
7851781, Dec 14, 2010
Filed:
Feb 13, 2009
Appl. No.:
12/378407
Inventors:
Mantu K. Hudait - Portland OR, US
Mohamad A. Shaheen - Portland OR, US
Loren A. Chow - Santa Clara CA, US
Peter G. Tolchinsky - Beaverton OR, US
Joel M. Fastenau - Bethlehem PA, US
Dmitri Loubychev - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 31/00
US Classification:
257 14, 257189, 257190, 257E29249
Abstract:
Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Stacking Fault And Twin Blocking Barrier For Integrating Iii-V On Si

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US Patent:
8617945, Dec 31, 2013
Filed:
Feb 3, 2012
Appl. No.:
13/366143
Inventors:
Mantu K. Hudait - Portland OR, US
Mohamad A. Shaheen - Portland OR, US
Loren A. Chow - Santa Clara CA, US
Peter G. Tolchinsky - Beaverton OR, US
Joel M. Fastenau - Bethlehem PA, US
Dmitri Loubychev - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/338
US Classification:
438172, 438 46, 438 47, 438 93, 438 94, 438191, 438938, 257190, 257200, 257201, 257615, 257E2109, 257E21097, 257E21098, 257E21108, 257E21109, 257E21112
Abstract:
A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10cmto be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
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Loren A Chow from Los Altos, CA, age ~55 Get Report