Larry D Mcmillan

6339238, Jan 15, 2002

Jun 10, 1999

09/329670

Myoungho Lim - Colorado Springs CO
Vikram Joshi - Colorado Springs CO
Joseph D. Cuchiaro - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO

H01L 2972

257295, 257296

A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.

6365927, Apr 2, 2002

Apr 3, 2000

09/541290

Joseph D. Cuchiaro - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO

H01L 2976

257295, 257 43

A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of metal oxide material in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following nitrides: aluminum titanium nitride (Al Ti N ), aluminum silicon nitride (Al Si N ), aluminum niobium nitride (AlNb N ), aluminum tantalum nitride (AlTa N ), aluminum copper nitride (Al Cu N ), tungsten nitride (WN), and copper nitride (Cu N ). The thin film of metal oxide is ferroelectric or high-dielectric, nonferroelectric material. Preferably, the metal oxide comprises ferroelectric layered superlattice material. Preferably, the hydrogen barrier layer is located directly over the thin film of metal oxide.

6370056, Apr 9, 2002

Mar 10, 2000

09/523492

Zheng Chen - Colorado Springs CO
Vikram Joshi - Colorado Springs CO
Myoungho Lim - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO

G11C 1122

365145, 36518508

A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line.

6373743, Apr 16, 2002

Aug 30, 1999

09/385308

Zheng Chen - Colorado Springs CO
Myoungho Lim - Colorado Springs CO
Vikram Joshi - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO

G11C 1122

365145, 365149

A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source.

6376691, Apr 23, 2002

Sep 1, 1999

09/388044

Jolanta Celinska - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Joseph D. Cuchiaro - Colorado Springs CO
Jeffrey W. Bacon - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO

C07F 1900

556 28, 556 42, 556 44, 556 51, 556 54, 556 55, 556 76, 556 77, 556 78, 556 81, 556105, 556442, 556482, 556483, 556 1, 2521823, 534 15

A liquid precursor for forming a transparent metal oxide thin film comprises a first organic precursor compound. In one embodiment, the liquid precursor is for making a conductive thin film. In this embodiment, the liquid precursor contains a first metal from the group including tin, antimony, and indium dissolved in an organic solvent. The liquid precursor preferably comprises a second organic precursor compound containing a second metal from the same group. Also, the liquid precursor preferably comprises an organic dopant precursor compound containing a metal selected from the group including niobium, tantalum, bismuth, cerium, yttrium, titanium, zirconium, hafnium, silicon, aluminum, zinc and magnesium. Liquid precursors containing a plurality of metals have a longer shelf life. The addition of an organic dopant precursor compound containing a metal, such as niobium, tantalum or bismuth, to the liquid precursor enhances control of the conductivity of the resulting transparent conductor.

6383555, May 7, 2002

Jul 13, 2000

09/615373

Shinichiro Hayashi - Osaka, JP
Larry D. McMillan - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO
Matsushita Electric Industrial Co., Ltd.

B05D 512

427 99, 427124, 4271263, 42725528, 42725531, 42725532, 4273831, 427901

A substrate is located within a deposition chamber, the substrate defining a substrate plane. A liquid precursor is misted by ultrasonic or venturi apparatus, to produce a colloidal mist. The mist is generated, allowed to settle in a buffer chamber, filtered through a system up to 0. 01 micron, and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film of solid material on the substrate, which is then incorporated into an electrical component of an integrated circuit.

6404003, Jun 11, 2002

Jul 28, 1999

09/362480

Larry D. McMillan - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Koji Arita - Colorado Springs CO
Masamichi Azuma - Shiga, JP

Symetrix Corporation - Colorado Springs CO
Matsushita Electric Industrial Co., Ltd.

H01L 27108

257306, 257310, 257311, 257532, 257535

An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400Â C. , and annealed at between 600Â C. and 850Â C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

6413883, Jul 2, 2002

Feb 3, 1999

09/243254

Shinichiro Hayashi - Osaka, JP
Larry D. McMillan - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO
Matsushita Electric Industrial Co., Ltd.

H01L 2131

438782, 438240, 438396, 4271263

A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.