Kwang Hui Kim

6424190, Jul 23, 2002

Sep 13, 2001

09/950572

Kwang Y. Kim - Irvine CA

Broadcom Corporation - Irvine CA

H03L 700

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6597216, Jul 22, 2003

Jul 19, 2002

10/197843

Kwang Y. Kim - Irvine CA

Broadcom Corporation - Irvine CA

H03L 700

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6791379, Sep 14, 2004

Dec 7, 1999

09/456230

Myles Wakayama - Laguna Niguel CA
Stephen A. Jantzi - Laguna Beach CA
Kwang Young Kim - Irvine CA
Yee Ling Felix Cheung - Irvine CA
Ka Wai Tong - Aliso Viejo CA

Broadcom Corporation - Irvine CA

H03L 706

327156

A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

6906564, Jun 14, 2005

Jul 21, 2003

10/622708

Kwang Y. Kim - Irvine CA, US

Broadcom Corporation - Irvine CA

H03L007/00

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6963245, Nov 8, 2005

Sep 3, 2003

10/653348

Josephus A. E. P. van Engelen - Aliso Viejo CA, US
Kwang Young Kim - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Broadcom Corporation - Irvine CA

H03F003/45

330259, 330253

A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

6975557, Dec 13, 2005

Apr 27, 2004

10/832262

Lionel J. D'Luna - Irvine CA, US
Mark Chambers - Mission Viejo CA, US
Thomas Hughes - Dana Point CA, US
Kwang Y. Kim - Irvine CA, US
Sathish K. Radhakrishnan - Karnataka, IN

Broadcom Corporation - Irvine CA

G11C008/00

365233, 365193, 365194

A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

6998885, Feb 14, 2006

Oct 7, 2004

10/959512

Kwang Y. Kim - Irvine CA, US

Broadcom Corporation - Irvine CA

H03L 7/00

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

7079535, Jul 18, 2006

Jul 27, 2001

09/917575

Kwang H. Kim - Irvine CA, US

The Regents of the Universtiy of California - Oakland CA

H04L 12/56

370390, 370242

The sender of a multicast in a computer network attaches an official release time to the message being multicast, asking every receiver to process the message at or after the official release time. A receiver may receive a cancellation notice after receiving the multicast message but before its official release time. The official release time is chosen so that the multicast can succeed or be cancelled by the official release time with the probability at or above a user selected level under reasonably bounded numbers of occurrences of permanent and temporary faults and reasonably bounded durations of temporary faults. This multicast protocol is formulated to suit the environment where it is not worth it for a node to wait for a reply from another node beyond a certain time-period, called the timeout period.