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Kuntal Joardar Phones & Addresses

  • 5124 Water Haven Ln, Plano, TX 75093
  • Colton, TX
  • 5911 Placita Primitiva, Tucson, AZ 85750
  • Chandler, AZ
  • Mesa, AZ
  • Tempe, AZ
  • 4698 W Carla Vista Dr, Chandler, AZ 85226

Work

Position: Service Occupations

Publications

Us Patents

Grooved Channel Schottky Mosfet

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US Patent:
6509609, Jan 21, 2003
Filed:
Jun 18, 2001
Appl. No.:
09/884345
Inventors:
Yaohui Zhang - Los Angeles CA
Kuntal Joardar - Chandler AZ
Daniel Thanh-Khac Pham - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2978
US Classification:
257330, 257369, 257384, 257407, 257412, 257476
Abstract:
A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 10 cm. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL0. 063) and the gate delay (CV/I) is reduced to 2. 4 ps.

Apparatus And Method For Modeling A Graded Channel Transistor

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US Patent:
56873557, Nov 11, 1997
Filed:
Aug 21, 1995
Appl. No.:
8/517046
Inventors:
Kuntal Joardar - Chandler AZ
Kiran Kumar Gullapalli - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 9455
G06F 1750
US Classification:
395500
Abstract:
The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.

Integrated Circuit Isolation Structure For Suppressing High-Frequency Cross-Talk

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US Patent:
56231598, Apr 22, 1997
Filed:
Apr 4, 1996
Appl. No.:
8/625685
Inventors:
David J. Monk - Gilbert AZ
Kuntal Joardar - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2704
US Classification:
257509
Abstract:
An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Lateral Bipolar Transistor Operating With Independent Base And Gate Biasing

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US Patent:
59364548, Aug 10, 1999
Filed:
Jun 1, 1993
Appl. No.:
8/069803
Inventors:
Kuntal Joardar - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 1760
US Classification:
327432
Abstract:
A laterally formed bipolar transistor receives independent base biasing at a base terminal and gate biasing at a gate terminal for providing high forward current gain and improved frequency response. The collector and emitter are formed with a first conductivity type and disposed in a well having a second conductivity type. The gate of the lateral transistor is formed adjacent to the well between the collector and emitter and receives the gate bias. The base of the lateral transistor is formed adjacent to the well and receiving the base bias. The combination of independent base and gate biasing provides more mobile carries to improve the forward current gain and frequency response of the lateral transistor while reducing its overall area.

Circuit Die Having Improved Substrate Noise Isolation

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US Patent:
54752558, Dec 12, 1995
Filed:
Jun 30, 1994
Appl. No.:
8/268744
Inventors:
Kuntal Joardar - Chandler AZ
Jeffrey D. Ganger - Austin TX
Sangil Park - Austin TX
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
H01L 2706
H01L 2941
US Classification:
257547
Abstract:
A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

Circuit And Method Of Reducing Cross-Talk In An Integrated Circuit Substrate

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US Patent:
59007630, May 4, 1999
Filed:
Oct 11, 1994
Appl. No.:
8/317673
Inventors:
Irfan Rahim - Selanger,
Bor-Yuan Hwang - Tempe AZ
Kuntal Joardar - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2126
US Classification:
327292
Abstract:
An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Semiconductor Structure And Method Of Manufacture

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US Patent:
62256742, May 1, 2001
Filed:
Apr 2, 1999
Appl. No.:
9/285532
Inventors:
Ik-Sung Lim - Gilbert AZ
David G. Morgan - Phoenix AZ
Kuntal Joardar - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2900
H01L 2976
H01L 2994
US Classification:
257506
Abstract:
A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the corresponding shielding structures (39, 40). A noise generating device is formed within a first shielding structure (43) and a noise sensitive device is formed within a second shielding structure (44). The two shielding structures (39, 40) are grounded and prevent noise from the noise generating device from interfering with the noise sensitive device.

Circuit And Method Of Varying Amplifier Gain

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US Patent:
54670578, Nov 14, 1995
Filed:
Oct 11, 1994
Appl. No.:
8/320427
Inventors:
Kuntal Joardar - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03F 345
H03G 330
US Classification:
330254
Abstract:
A variable gain amplifier (10) provides a controllable amplification of an input signal as determined by a gate voltage. The variable gain amplifier takes on the form of a differential amplifier with first and second emitter-coupled lateral NPN bipolar transistors (12, 26) each having a gate (60) spanning the base region (48). The bases of the first and second transistors are biased with resistors (20-22, 30-32) coupled between V. sub. cc and ground potential. The gate voltage effects the conductivity through the base region and provides control over the forward current gain of the transistors. A third lateral NPN bipolar transistor (70) is added in parallel with the first transistor and operates with a separate gate voltage to provide two modes of amplification.
Kuntal Joardar from Plano, TX, age ~59 Get Report