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Kunal B Shrotri

from Boise, ID
Age ~44
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Related to:
Aparna U Limaye, 42
Connected to:
Mugdha S Shrotriya, 43Caleb M Shrout, 41Crystal Shrout, 42Diana G Shrout, 70Donnie Shrout, 38Elizabeth A Shrout, 59John D Shrout, 76Kayla E Shrout, 33Ronald H Shrout, 72Stacey M Shrout, 39

Kunal Shrotri Phones & Addresses

  • Boise, ID
  • Rochester, NY
  • 4297 S Redhawk Pl, Boise, ID 83716

Work

Company: Micron technology Sep 2010 Position: R&d thin films process engineer

Education

Degree: Engineering Management School / High School: University of Colorado at Boulder 2008 to 2012 Specialities: Quality Systems and Engineering

Skills

Semiconductors • Thin Films • Semiconductor Industry • Design of Experiments • Materials Science • Spc • Failure Analysis • Process Simulation • Characterization • Lean Manufacturing • Cross Functional Team Leadership • Silicon • Jmp • Six Sigma • Polymers

Industries

Semiconductors

Resumes

Resumes

Kunal Shrotri Photo 1

Film R And D Section Manager

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology since Sep 2010
R&D Thin Films Process Engineer
Micron Technology Mar 2006 - Sep 2010
Process Engineer
General Electric Nov 2005 - Feb 2006
Polymer Research Intern
Vardhman Plastics Jul 2002 - Jul 2003
Polymer Engineer
Education:
University of Colorado at Boulder 2008 - 2012
Engineering Management, Quality Systems and Engineering Rochester Institute of Technology 2003 - 2006
MS - Material Science and Engineering, Composite Material Systems Maharashtra Institute of Technology 1998 - 2002
Bachelor's degree, Polymer/Plastics Engineering
Skills:
Semiconductors
Thin Films
Semiconductor Industry
Design of Experiments
Materials Science
Spc
Failure Analysis
Process Simulation
Characterization
Lean Manufacturing
Cross Functional Team Leadership
Silicon
Jmp
Six Sigma
Polymers

Publications

Us Patents

Dram Cells And Methods Of Forming Silicon Dioxide

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US Patent:
20130277723, Oct 24, 2013
Filed:
Apr 19, 2012
Appl. No.:
13/451316
Inventors:
Shivani Srivastava - Boise ID, US
Kunal Shrotri - Boise ID, US
Fawad Ahmed - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 27/108
H01L 21/302
H01L 21/336
H01L 21/316
US Classification:
257296, 438788, 438771, 438696, 438270, 257E21279, 257E21285, 257E21214, 257E21409
Abstract:
Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000 C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050 C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000 C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050 C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

Semiconductor Devices With Liners And Related Methods

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US Patent:
20220278214, Sep 1, 2022
Filed:
May 20, 2022
Appl. No.:
17/664279
Inventors:
- Boise ID, US
David A. Daycock - Singapore, SG
Kunal Shrotri - Boise ID, US
International Classification:
H01L 29/423
H01L 21/308
H01L 27/11517
H01L 21/28
H01L 27/11521
H01L 21/3213
H01L 27/11558
H01L 29/06
H01L 29/788
Abstract:
Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

Microelectronic Devices Including Stair Step Structures, And Related Electronic Devices And Methods

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US Patent:
20220271051, Aug 25, 2022
Filed:
May 3, 2022
Appl. No.:
17/661781
Inventors:
- Boise ID, US
Kunal Shrotri - Boise ID, US
Matthew J. King - Boise ID, US
International Classification:
H01L 27/11556
H01L 27/11519
H01L 27/11582
H01L 27/11565
H01L 27/1157
H01L 27/11524
H01L 21/768
H01L 27/11548
Abstract:
A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

Microelectronic Devices Including Tiered Stacks Including Conductive Structures Isolated By Slot Structures, And Related Electronic Systems And Methods

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US Patent:
20220199641, Jun 23, 2022
Filed:
Dec 18, 2020
Appl. No.:
17/127971
Inventors:
- Boise ID, US
Jun Fujiki - Tokyo, JP
Matthew J. King - Boise ID, US
Sidhartha Gupta - Boise ID, US
Paolo Tessariol - Arcore, IT
Kunal Shrotri - Boise ID, US
Kye Hyun Baek - Boise ID, US
Kyle A. Ritter - Boise ID, US
Shuji Tanaka - Tokyo, JP
Umberto Maria Meotto - Rivoli, IT
Richard J. Hill - Boise ID, US
Matthew Holland - Boise ID, US
International Classification:
H01L 27/11582
H01L 27/11556
Abstract:
A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

Integrated Assemblies And Methods Of Forming Integrated Assemblies

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US Patent:
20220181334, Jun 9, 2022
Filed:
Feb 23, 2022
Appl. No.:
17/678983
Inventors:
- Boise ID, US
Kunal Shrotri - Boise ID, US
Matthew Thorum - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/1157
H01L 27/11524
H01L 27/11582
H01L 27/11556
H01L 27/11565
H01L 27/11519
Abstract:
Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Methods Of Forming Electronic Devices Using Materials Removable At Different Temperatures

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US Patent:
20230061820, Mar 2, 2023
Filed:
Oct 17, 2022
Appl. No.:
18/047214
Inventors:
- Boise ID, US
Kunal Shrotri - Boise ID, US
International Classification:
H01L 27/11556
H01L 27/11585
Abstract:
A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

Integrated Assemblies And Methods Of Forming Integrated Assemblies

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US Patent:
20210391352, Dec 16, 2021
Filed:
Jun 16, 2020
Appl. No.:
16/902897
Inventors:
- Boise ID, US
Jeslin J. Wu - Boise ID, US
Chandra Tiwari - Boise ID, US
Kunal Shrotri - Boise ID, US
Swapnil Lengade - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11582
H01L 27/11524
H01L 27/11556
H01L 27/1157
H01L 21/02
H01L 21/3115
H01L 21/311
Abstract:
Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Methods Of Forming Electronic Devices Using Materials Removable At Different Temperatures

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US Patent:
20210375898, Dec 2, 2021
Filed:
May 29, 2020
Appl. No.:
16/887178
Inventors:
- Boise ID, US
Kunal Shrotri - Boise ID, US
International Classification:
H01L 27/11556
H01L 27/11585
Abstract:
A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.
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Kunal B Shrotri from Boise, ID, age ~44 Get Report