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Krishna V Palem

from Houston, TX
Age ~66
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Also known as:
Krishna V Palme, Palem Z Krishna
Phone and address:
2001 Holcombe Blvd UNIT 3902, Houston, TX 77030
Related to:
So Palem
Connected to:
Apryl A Palen, 70Brad Palen, 58Dean N Palen, 73Denise A Palen, 59Desiderio R Palen, 53Dirk W Palen, 81Eric L Palen, 58Gabriel C Palen, 42Judy A Palen, 69Julie A Palen, 37

Krishna Palem Phones & Addresses

  • 2001 Holcombe Blvd UNIT 3902, Houston, TX 77030
  • Pasadena, CA
  • 85 5Th St NW #D, Atlanta, GA 30308
  • 3226 Post Woods Dr, Atlanta, GA 30339
  • New York, NY

Work

Company: Rice university Position: Professor

Industries

Higher Education

Resumes

Resumes

Krishna Palem Photo 1

Professor

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Location:
Houston, TX
Industry:
Higher Education
Work:
Rice University
Professor

Business Records

Name / Title
Company / Classification
Phones & Addresses
Krishna V Palem
PROGRAMMING TOOLS AND TECHNOLOGIES CORP
C/O Palmeri & Gaven 55 John St, New York, NY 10038

Publications

Wikipedia References

Krishna Palem Photo 2

Krishna Palem

Work:
Company:

New York University faculty • Georgia Institute of Technology faculty • Rice University faculty

Position:

Chief technology officer

Education:
Area of science:

Compilers • Architecture

Specialty:

Director • Compiler

Academic degree:

Professor • PHD

Professions and applied sciences:

Compilers

Skills & Activities:
Skill:

Software • Instruction • Algorithms

Us Patents

Variable Scaling For Computing Elements

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US Patent:
8316249, Nov 20, 2012
Filed:
Feb 15, 2008
Appl. No.:
12/527211
Inventors:
Krishna V. Palem - Atlanta GA, US
Bilge E. Akgul - Istanbul, TR
Jason M. George - Acworth GA, US
Harry Bourne Marr - Atlanta GA, US
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
G06F 1/26
G06F 1/32
US Classification:
713320, 713300, 713322, 713323, 713324, 714 1
Abstract:
Various systems, methods, and computing units are provided for variable scaling of computing elements. In one representative embodiment, a method comprises: receiving a plurality of computing resource levels; and providing one of the plurality of computing resource levels to each of a plurality of computing elements, each computing element having an associated output, the provided voltage level based upon associated output significance.

Computing Device Using Inexact Computing Architecture Processor

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US Patent:
8589742, Nov 19, 2013
Filed:
Mar 9, 2010
Appl. No.:
13/254029
Inventors:
Krishna V. Palem - Houston TX, US
Lakshmi Narasimhan Chakrapani - Houston TX, US
Avinash Lingamneni - Houston TX, US
Assignee:
William Marsh Rice University - Houston TX
International Classification:
G06F 11/00
US Classification:
714 471
Abstract:
In general, in one aspect, the invention relates to a computer readable medium including software instructions which, when executed by a processor, perform a method, the method including receiving a first method call from an application, wherein the first method call is associated with a first application component; obtaining a first application component error tolerance (ACET) value associated with the first method call; determining, using the first ACET value and a first inexact amount value (IAV) of a first inexact computing architecture (ICA) processor, that the first ICA processor is available to execute the first method call; and processing the first method call using the first ICA processor.

Parameterized Application Programming Interface For Reconfigurable Computing Systems

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US Patent:
20020174266, Nov 21, 2002
Filed:
May 18, 2001
Appl. No.:
09/860942
Inventors:
Krishna Palem - Atlanta GA, US
Hitesh Patel - Atlanta GA, US
Sudhakar Yalamanchili - Marietta GA, US
International Classification:
G06F009/00
US Classification:
709/328000
Abstract:
The invention affords a system and method for programming a data processor having a microprocessor and reconfigurable logic, to attain high-speed performance while maintaining compatibility with current software programming practices by providing an API that makes the details of the interaction between the microprocessor and the reconfigurable logic units transparent to the compiler. The API virtualizes operations implemented within the reconfigurable logic unit as reconfigurable logic instructions (RL-instructions) which can be scheduled by the compiler in a manner similar to microprocessor instructions. The API provides methods for the microprocessor to configure the reconfigurable logic unit, transmit data to the reconfigurable logic unit, receive data from the reconfigurable logic unit, and otherwise interact with the reconfigurable logic unit. The set of functions that constitute the API are independent of a particular microprocessor, reconfigurable logic unit, number of reconfigurable logic units, or implementation of the API. The API implementation translates hardware dependent instructions into a set of functions that affords an implementation independent interface across all potential reconfigurable logic units. Thus, the present invention enables programming of microprocessors interacting with reconfigurable logic units using current software design processes to optimize the use of associated reconfigurable logic units.

Probabilistic And Introverted Switching To Conserve Energy In A Digital System

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US Patent:
20050240787, Oct 27, 2005
Filed:
Apr 27, 2005
Appl. No.:
11/115651
Inventors:
Krishna Palem - Atlanta GA, US
Suresh Cheemalavagu - Marietta GA, US
Pinar Korkmaz - Istanbul, TR
Bilge Akgul - Istanbul, TR
International Classification:
G06F001/26
US Classification:
713320000
Abstract:
A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Camera-Based Positioning System Using Learning

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US Patent:
20200256679, Aug 13, 2020
Filed:
Aug 28, 2017
Appl. No.:
16/327900
Inventors:
Anshumali Shrivastava - Houston TX, US
Chen Luo - Houston TX, US
Krishna Palem - Houston TX, US
Yongshik Moon - Seoul, KR
Soonhyun Noh - Seoul, KR
Daedong Park - Seoul, KR
Seongsoo Hong - Seoul, KR
International Classification:
G01C 21/20
G06T 7/73
G06K 9/62
G06N 20/00
G06F 16/51
G06F 16/532
Abstract:
A device, system, and methods are described to perform machine-learning camera-based indoor mobile positioning. The indoor mobile positioning may utilize inexact computing, wherein a small decrease in accuracy is used to obtain significant computational efficiency. Hence, the positioning may be performed using a smaller memory overhead at a faster rate and with lower energy cost than previous implementations. The positioning may not involve any communication (or data transfer) with any other device or the cloud, providing privacy and security to the device. A hashing-based image matching algorithm may be used which is cheaper, both in energy and computation cost, over existing state-of-the-art matching techniques. This significant reduction allows end-to-end computation to be performed locally on the mobile device. The ability to run the complete algorithm on the mobile device may eliminate the need for the cloud, resulting in a privacy-preserving localization algorithm by design since network communication with other devices may not be required.

Addressable Siox Memory Array With Incorporated Diodes

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US Patent:
20160276411, Sep 22, 2016
Filed:
Jun 2, 2016
Appl. No.:
15/171196
Inventors:
James M. Tour - Bellaire TX, US
Jun Yao - Allston MA, US
Jian Lin - Houston TX, US
Krishna Palem - Houston TX, US
Assignee:
William Marsh Rice University - Houston TX
International Classification:
H01L 27/24
H01L 29/872
H01L 29/861
H01L 45/00
Abstract:
Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiO, SiON, SiONH, SiOC, SiOCH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.
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Krishna V Palem from Houston, TX, age ~66 Get Report