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Kiran Kumar Gullapalli

from Austin, TX
Age ~56
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Also known as:
Kiran K Gullapalli, Kiran Kum Gullapalli, Kirankumar K Gullapalli, Kiran Kumar Gullapa, Krian K Gullapalli, Kiran Kumar
Phone and address:
2009 Cerca Viejo Way, Austin, TX 78746
(512) 412-2078
Related to:
Ajit N Kumar, 68Madhulika Kumar, 55Karishma Kumar, 29Kamlesh Kumar, 81Spiram Kumar, 48Singh Lachman, 44
Connected to:
Deekshitulu K Gullapalli, 55Janardhana R Gullapalli, 73Lavanya Gullapalli, 50Michelle R Gullap, 58Rachita Gullapalli, 51Sireesha Gullapalli, 44Blake E Gullatte, 36Carol S Gullatt, 55Hillary D Gullatt, 43Joyce Gullatte, 55

Kiran Gullapalli Phones & Addresses

  • 2009 Cerca Viejo Way, Austin, TX 78746 (512) 412-2078
  • 11701 Metric Blvd, Austin, TX 78758
  • Dripping Springs, TX
  • Travis, TX
  • 8907 Turks Cap Cv, Austin, TX 78750 (512) 757-2571

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: High school graduate or higher

Emails

k***[email protected]

Resumes

Resumes

Kiran Gullapalli Photo 1

Circuit Simulation R&D

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Location:
Austin, Texas Area
Industry:
Semiconductors
Kiran Gullapalli Photo 2

Fellow

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor - Austin, Texas Area since Mar 2008
Distinguished Member of Technical Staff
Freescale Inc - Austin, Texas Area May 2005 - Mar 2008
Senior Member of Technical Staff
Synopsys - Austin, Texas Area Apr 2002 - May 2005
Senior Staff R&D Engineer
Motorola - Austin, Texas Area 1994 - 2002
Senior Member of Technical staff
Education:
The University of Texas at Austin - The Red McCombs School of Business 2007 - 2009
MBA, General Management The University of Texas at Austin 1991 - 1994
PhD, Electrical and Computer Engineering The University of Texas at Austin 1989 - 1991
MS, Electrical and Computer Engineering Indian Institute of Technology, Madras 1985 - 1989
BTech, Electrical Engineering
Skills:
Simulations
Algorithms
Semiconductors
Rf
Eda
Ic
Asic
High Performance Computing
Mixed Signal
Soc
Software Development
Analog
Cmos
Verilog
Debugging
Analog Simulation
C
Vlsi
Sparse Matrix Methods
Rf Simulation
Circuit Simulation
Engineering Management
Physics
Microprocessors
Circuit Design
Analog Circuit Design
Integrated Circuit Design
Application Specific Integrated Circuits
Device Physics
Processors
Integrated Circuits
Radio Frequency
Static Timing Analysis
Simulation
High Performance Computing
Interests:
Science and Technology
Children
Education
Kiran Gullapalli Photo 3

Kiran Gullapalli

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Skills:
Talent Acquisition
Kiran Gullapalli Photo 4

Kiran Gullapalli

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Publications

Us Patents

Method And Apparatus For Analyzing Small Signal Response And Noise In Nonlinear Circuits

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US Patent:
6536026, Mar 18, 2003
Filed:
Jun 30, 2001
Appl. No.:
09/896079
Inventors:
Kiran K. Gullapalli - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1750
US Classification:
716 6, 716 1, 716 4, 716 10
Abstract:
The present invention relates generally to analyzing small signal response and noise in nonlinear circuits. One embodiment relates to a computer implemented method for analyzing an electrical circuit. The method includes receiving a circuit description and circuit element models, generating circuit equations using the circuit description and models, and determining a periodic stead-state response of the electrical circuit in the time domain. The method further includes linearizing the circuit element models about the steady-state response, generating a time-varying linear system of equations, and representing a small signal solution to the time-varying linear system of equations in response to a sine wave input as an amplitude modulated sine wave. The method also includes discretizing the time-varying linear system of equations by discretizing only the amplitude modulation of the small signal solution and performing a time-varying small signal analysis of the electrical circuit using the discretized equations.

Method And Apparatus For Distortion Analysis In Nonlinear Circuits

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US Patent:
7007253, Feb 28, 2006
Filed:
Sep 8, 2003
Appl. No.:
10/657304
Inventors:
Kiran K. Gullapalli - Austin TX, US
Mark M. Gourary - Moscow, RU
Sergei G. Rusakov - Moscow, RU
Sergei L. Ulyanov - Moscow, RU
Mikhail M. Zharov - Moscow, RU
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 716 6
Abstract:
A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.

Automatic, Hierarchy-Independent Partitioning Method For Transistor-Level Circuit Simulation

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US Patent:
8060355, Nov 15, 2011
Filed:
Jul 27, 2007
Appl. No.:
11/829844
Inventors:
Kevin J. Kerns - San Jose CA, US
Mayukh Bhattacharya - Fremont CA, US
Svetlana Rudnaya - San Jose CA, US
Kiran Gullapalli - Austin TX, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 14, 716 1
Abstract:
A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Circuit Simulation Acceleration Using Model Caching

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US Patent:
20130054217, Feb 28, 2013
Filed:
Aug 22, 2011
Appl. No.:
13/214827
Inventors:
Kiran Kumar Gullapalli - Austin TX, US
Steven D. Hamm - Austin TX, US
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.

Apparatus And Method For Modeling A Graded Channel Transistor

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US Patent:
56873557, Nov 11, 1997
Filed:
Aug 21, 1995
Appl. No.:
8/517046
Inventors:
Kuntal Joardar - Chandler AZ
Kiran Kumar Gullapalli - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 9455
G06F 1750
US Classification:
395500
Abstract:
The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.

Method Of Simulating An Integrated Circuit

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US Patent:
57991723, Aug 25, 1998
Filed:
Sep 10, 1996
Appl. No.:
8/711638
Inventors:
Kiran Kumar Gullapalli - Austin TX
Brian J. Mulvaney - Austin TX
Steven D. Hamm - Austin TX
Steven R. Beckerich - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06G 748
US Classification:
395500
Abstract:
A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.

Semiconductor Device Apparatus Having Multiple Current-Voltage Curves And Zero-Bias Memory

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US Patent:
54081076, Apr 18, 1995
Filed:
May 20, 1993
Appl. No.:
8/065343
Inventors:
Dean P. Neikirk - Austin TX
Kiran K. Gullapalli - Austin TX
Assignee:
The Board of Regents of the University of Texas System - Austin TX
International Classification:
H01L 2712
H01L 4800
H01L 4902
US Classification:
257 28
Abstract:
Heterostructure barrier quantum well device with a super-lattice structure of alternating lightly doped and heavily doped spacer layers having multiple, stable current-voltage curves extending continuously through zero bias at ambient temperature. The device can be repetitively switched between the multiple current-voltage curves. Once placed on a particular curve, the device retains memory of the curve it has been set on, even if held at zero bias for extended periods of time. The device can be switched between current-voltage curve settings at higher positive or negative voltages and can be read at lower voltages. Switching between current-voltage curve settings can also be effected by additional terminal connection(s) to the spacer layer(s).

Method And Apparatus To Facilitate Simulating A Circuit Connected To A Multiport Interconnect Structure

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US Patent:
20150213171, Jul 30, 2015
Filed:
Jan 29, 2014
Appl. No.:
14/167671
Inventors:
Kiran Kumar Gullapalli - Austin TX, US
Assignee:
FREESCALE SEMICONDUCTOR, INC. - Austin TX
International Classification:
G06F 17/50
Abstract:
A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.
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Kiran Kumar Gullapalli from Austin, TX, age ~56 Get Report