Kent A Ponton

6876319, Apr 5, 2005

Nov 27, 2002

10/306020

Mark A. Webster - Indian Harbour Beach FL, US
Kent A. Ponton - Palm Bay FL, US

Intersil Americas Inc. - Irvine CA

H03M003/00

341143, 341 61

An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples.

20020075617, Jun 20, 2002

Dec 19, 2000

09/741221

Kent Ponton - Palm Bay FL, US
James Swonger - Palm Bay FL, US

Intersil Corporation

H02H009/00

361/091100, 361/058000, 361/091500

A circuit architecture provides overvoltage protection for a bidirectional transmission gate of complementary polarity field effect transistors. In a first embodiment, a single auxiliary clamping MOS device is coupled in circuit with the input path, as long as there is a defined output and only the input is subject to the possibility of an overvoltage condition. When the voltage applied to the input port exceeds the supply voltage by the MOS gate threshold, the auxiliary clamping MOS transistor is turned on, pulling the voltage applied to the gate of the transmission gate FET very close to the applied overvoltage level by a voltage differential that is less than a diode drop. This reduction in Vgs of the transmission gate MOSFET reduces its source-to-drain current, as the MOS device operates deeper in a sub-threshold region, increasing the overvoltage rating for the same leakage current specification. In a second embodiment, a clamping MOS device is coupled on either side of the source-drain path of the transmission gate's MOS device. In addition, rather than coupling the gate of a respective clamping device to the supply voltage terminal as in the first embodiment, the gates of the clamping devices are coupled in circuit with and controlled by associated clamping control MOS devices, so that only the clamping device on the side of the transmission gate encountering the overvoltage condition will be turned on, whereas the clamping device on the opposite side of the transmission gate will be held off.