Resumes
Resumes
Design Verification Engineer
View pageLocation:
Austin, TX
Industry:
Semiconductors
Work:
Amd Mar 2011 - Dec 2012
Design Verification Engineer
Apple Mar 2011 - Dec 2012
Design Verification Engineer
Interdigital Communications Jan 2010 - Mar 2011
Intern
Temple University Oct 2008 - Dec 2009
Research Assistant
Temple University Sep 2008 - Dec 2008
Adjunct Instructor
Design Verification Engineer
Apple Mar 2011 - Dec 2012
Design Verification Engineer
Interdigital Communications Jan 2010 - Mar 2011
Intern
Temple University Oct 2008 - Dec 2009
Research Assistant
Temple University Sep 2008 - Dec 2008
Adjunct Instructor
Education:
Temple University 2008 - 2010
Masters, Master of Science In Electrical Engineering, Electrical Engineering
Masters, Master of Science In Electrical Engineering, Electrical Engineering
Skills:
Digital Design Verification
Excellent Skills In Object Oriented Programming Using C++
Solid Background In Computer Architecture
Verilog
Pspice
Vhdl
Matlab
C
Multisim
C++
Ovm
System Verilog
Functional Verification
Perl
Systemverilog
Hardware Architecture
Excellent Skills In Object Oriented Programming Using C++
Solid Background In Computer Architecture
Verilog
Pspice
Vhdl
Matlab
C
Multisim
C++
Ovm
System Verilog
Functional Verification
Perl
Systemverilog
Hardware Architecture
Interests:
Reading Journal Papers
Exploring New Technology
Gardening
Exploring New Technology
Gardening