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Karim S Boutros

from Moorpark, CA
Age ~58
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Also known as:
Karim Samy Boutros, Karim S Bourtos, Samy Boutros Karim, Boutros Karim
Phone and address:
11976 Bubbling Brook St, Moorpark, CA 93021
(805) 553-0457
Related to:
Marie Boutros
Connected to:
Antoine A Boutros, 68Bedeir Z Boutros, 74Chantal Boutros, 46Christina R Boutros, 38Elias Boutros, 44Francisco J Boutros, 52Hasnaa Boutros, 52Kareen W Boutros, 55Kelly N Boutross, 37Marc Boutros, 35

Karim Boutros Phones & Addresses

  • 11976 Bubbling Brook St, Moorpark, CA 93021 (805) 553-0457
  • 20 Pembroke Rd, Danbury, CT 06811 (203) 743-9452
  • 11 Edinburgh Dr, Peekskill, NY 10566 (845) 737-7953
  • Raleigh, NC
  • Simi Valley, CA
  • Greenville, NC
  • Ventura, CA
  • 11976 Bubbling Brook St, Moorpark, CA 93021 (805) 794-9462

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

k***[email protected]

Resumes

Resumes

Karim Boutros Photo 1

Senior Technology Qualification Engineer

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Location:
Moorpark, CA
Industry:
Semiconductors
Work:
Boeing
Senior Technology Qualification Engineer
Stmicroelectronics Aug 1, 2015 - Aug 2018
Technology Development Director
Hrl Laboratories, Llc Mar 2010 - Jul 2015
Manager, Energy Efficient Electronics
Hrl Laboratories, Llc Mar 1, 2008 - Feb 1, 2010
Senior Research Scientist
Teledyne Technologies Incorporated Aug 2001 - Jan 2008
Prinicipal Scientist
Education:
North Carolina State University Jan 1, 1990 - Dec 31, 1996
Doctorates, Doctor of Philosophy, Electronics Engineering, Electronics Alexandria University
Skills:
Semiconductors
R&D
Nanotechnology
Electronics
Silicon
Failure Analysis
Sensors
Optoelectronics
Microelectronics
Engineering Management
Product Development
Semiconductor Industry
Rf
Photovoltaics
Power Electronics
Research and Development
Solar Cells
Semiconductor Device
Microfabrication
Circuit Design
Nanofabrication
Renewable Energy
Solar Energy
Thin Films
Program Management
Physics
Languages:
French
Arabic
English
Karim Boutros Photo 2

Karim Boutros

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Publications

Us Patents

Monolithic Bypass-Diode And Solar-Cell String Assembly

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US Patent:
6635507, Oct 21, 2003
Filed:
Jul 14, 1999
Appl. No.:
09/353526
Inventors:
Karim S. Boutros - Moorpark CA
Dmitri D. Krut - Encino CA
Nasser H. Karam - Northridge CA
Assignee:
Hughes Electronics Corporation - El Segundo CA
International Classification:
H01L 2100
US Classification:
438 57, 438 59, 438 64, 438 66, 136243, 136244, 136258
Abstract:
An apparatus and method are described for making a solar cell with an integrated bypass diode. The method comprises the steps of depositing a second layer having a first type of dopant on a first layer having an opposite type of dopant to the first type of dopant to form a solar cell, depositing a third layer having the first type of dopant on the second layer, depositing a fourth layer having the opposite type of dopant on the third layer, the third layer and fourth layer forming a bypass diode, selectively etching the third layer and the fourth layer to expose the second layer and the third layer, and applying contacts to the fourth layer, third layer, and the first layer to allow electrical connections to the assembly. The apparatus comprises a first layer having a first type of dopant, a second layer having a second type of dopant opposite to the first type of dopant, wherein the first layer and the second layer form a solar cell, a third layer, coupled to the second layer, and a fourth layer, coupled to the third layer, the third layer and the fourth layer forming a bypass diode.

Integrated Semiconductor Circuits On Photo-Active Germanium Substrates

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US Patent:
7151307, Dec 19, 2006
Filed:
Nov 20, 2003
Appl. No.:
10/718426
Inventors:
Karim S. Boutros - Moorpark CA, US
Nasser H. Karam - Northridge CA, US
Dimitri D. Krut - Encino CA, US
Moran Haddad - Winnetka CA, US
Assignee:
The Boeing Company - Chicago IL
International Classification:
H01L 31/0328
H01L 31/117
US Classification:
257616, 257189, 257201, 257613
Abstract:
A semiconductor device having at least one layer of a group III–V semiconductor material epitaxially deposited on a group III–V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III–V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

Gallium Nitride Switch Methodology

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US Patent:
7893791, Feb 22, 2011
Filed:
Oct 22, 2008
Appl. No.:
12/256321
Inventors:
Yin Tat Ma - Thousand Oaks CA, US
Jonathan Hacker - Thousand Oaks CA, US
Karim S. Boutros - Malibu CA, US
Assignee:
The Boeing Company - Chicago IL
International Classification:
H01P 1/10
H01P 5/12
US Classification:
333104, 333134
Abstract:
Devices and systems for using a Gallium Nitride-based (GaN-based) transistor for selectively switching signals are provided. A first transmission line is configured to connect a common connection and a first connection. A first Gallium-Nitride-based (GaN-based) transistor has a first terminal coupled to the first transmission line at a first point, a second terminal coupled to a relative ground, and a third terminal configured to be coupled to a first control connection. A second GaN-based transistor has a first terminal coupled to the first transmission line at a second point, a second terminal configured to be coupled to the relative ground, and a third terminal configured to be coupled to the first control connection.

Two Stage Plasma Etching Method For Enhancement Mode Gan Hfet

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US Patent:
8124505, Feb 28, 2012
Filed:
Oct 21, 2010
Appl. No.:
12/909497
Inventors:
Shawn D Burnham - Oxnard CA, US
Karim S. Boutros - Moorpark CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/20
H01L 21/36
H01L 31/20
US Classification:
438483, 438172, 257E21407, 257E2145
Abstract:
A two stage plasma etching technique is described that allows the fabrication of an enhancement mode GaN HFET/HEMT. A gate recess area is formed in the Aluminum Gallium Nitride barrier layer of an GaN HFET/HEMT. The gate recess is formed by a two stage etching process. The first stage of the technique uses oxygen to oxidize the surface of the Aluminum Gallium Nitride barrier layer below the gate. Then the second stage uses Boron tricloride to remove the oxidized layer. The result is a self limiting etch process that uniformly thins the Aluminum Gallium Nitride layer below the HFET's gate region such that the two dimensional electron gas is not formed below the gate, thus creating an enhancement mode HFET.

High Current High Voltage Gan Field Effect Transistors And Method Of Fabricating Same

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US Patent:
8530978, Sep 10, 2013
Filed:
Dec 6, 2011
Appl. No.:
13/312406
Inventors:
Rongming Chu - Calabasas CA, US
Zijian “Ray” Li - Oak Park CA, US
Karim S. Boutros - Moorpark CA, US
Shawn Burnham - Oxnard CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 29/66
US Classification:
257409, 257289, 257192, 257194, 257401, 438191, 438590
Abstract:
A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET including a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact, and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.

Monolithic Bypass-Diode And Solar-Cell String Assembly

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US Patent:
20020164834, Nov 7, 2002
Filed:
Apr 29, 2002
Appl. No.:
10/134191
Inventors:
Karim Boutros - Moorpark CA, US
Dmitri Krut - Encino CA, US
Nasser Karam - Northridge CA, US
International Classification:
H01L021/00
US Classification:
438/059000
Abstract:
An apparatus and method for making a solar cell with an integrated bypass diode. The method comprises the steps of depositing a second layer having a first type of dopant on a first layer having an opposite type of dopant to the first type of dopant to form a solar cell, depositing a third layer having the first type of dopant on the second layer, depositing a fourth layer having the opposite type of dopant on the third layer, the third layer and fourth layer forming a bypass diode, selectively etching the third layer and the fourth layer to expose the second layer and the third layer, and applying contacts to the fourth layer, third layer, and the first layer to allow electrical connections to the assembly. The apparatus comprises a first layer having a first type of dopant, a second layer having a second type of dopant opposite to the first type of dopant, wherein the first layer and the second layer form a solar cell, a third layer, coupled to the second layer, and a fourth layer, coupled to the third layer, the third layer and the fourth layer forming a bypass diode.

Semiconductor Circuits And Devices On Germanium Substrates

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US Patent:
20020168809, Nov 14, 2002
Filed:
May 8, 2001
Appl. No.:
09/850773
Inventors:
Karim Boutros - Moorpark CA, US
Nasser Karam - Northridge CA, US
Dimitri Krut - Encino CA, US
Moran Haddad - Winnetka CA, US
International Classification:
H01L029/06
H01L031/0328
US Classification:
438/169000, 257/019000, 257/021000, 257/013000, 257/552000, 438/192000, 438/172000, 438/519000
Abstract:
A semiconductor device having at least one layer of a group III-V semiconductor material epitaxially deposited on a group III-V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III-V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

Quasi-Optical Array Amplifier

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US Patent:
20060139739, Jun 29, 2006
Filed:
Nov 30, 2004
Appl. No.:
10/956231
Inventors:
J. Higgins - Westlake Village CA, US
Avijit Bhunia - Thousand Oaks CA, US
Karim Boutros - Moorpark CA, US
International Classification:
H01S 3/00
US Classification:
359333000
Abstract:
The present invention is an array amplifier designed to alleviate thermal limitations and to provide better power combining efficiency for an array of high power density semiconductor devices. A semiconductor device having an aggregate size required to provide a desired output power is split into many small thermally isolated “unit cells”, each of which is equipped with antennas for input and for output. Power is combined ‘spatially’ off-chip, with each small unit cell operating at a moderate temperature which will not adversely affect performance.
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Karim S Boutros from Moorpark, CA, age ~58 Get Report