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Karanam K Balasubramanyam

from Hopewell Junction, NY
Age ~82
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Also known as:
Karanam K Balasubramanyan, Balasubramanyam Dr Karanam, Bala Subramanyam Karanam, Karanam Balasubrama, Karanam M, Balasubram Karanam, Kara Balasubram
Phone and address:
14 Marges Way, East Fishkill, NY 12533
(845) 226-7642
Related to:
Vickie HartwigLalitha Balasubramanyam, 53L Balasubramanyam, 53Hanen Baali, 37Amala Karanam Balasubramanyam, 74A K Balasubramanyam, 74Gowri Pachigolla, 45Naveen Balasubramanyam, 51
Connected to:
Ajay Balasubramaniam, 45Aravind Balasubramanian, 45Ashok Balasubramanian, 47Ashok Balasubramaniam, 44Barath Balasubramanian, 45Deepa Balasubramanayam, 48Hari Balasubramanian, 45Hari Balasubramaniam, 51Kavitha Balasubramanian, 51Kavitha Balasubramaniam, 42

Karanam Balasubramanyam Phones & Addresses

  • 14 Marges Way, Hopewell Junction, NY 12533 (845) 226-7642
  • 14 Marges Way #B, Hopewell Junction, NY 12533 (845) 226-7642
  • 6 Marges Way, Hopewell Junction, NY 12533
  • East Fishkill, NY
  • Wappingers Falls, NY
  • Port Jefferson Station, NY

Resumes

Resumes

Karanam Balasubramanyam Photo 1

Consultant

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Location:
14 Marges Way, Hopewell Junction, NY 12533
Industry:
Legal Services
Work:

Consultant
Karanam Balasubramanyam Photo 2

Karanam Balasubramanyam

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Publications

Us Patents

Method Of Forming An Oxide Film On A Gate Side Wall Of A Gate Structure

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US Patent:
6605521, Aug 12, 2003
Filed:
Oct 8, 2002
Appl. No.:
10/265729
Inventors:
Atul C. Ajmera - Wappingers Falls NY
Karanam Balasubramanyam - Hopewell Junction NY
Tomio Katata - Yokohama, JP
Shang-Bin Ko - Poughkeepsie NY
Assignee:
Kabushiki Kaisha Toshiba - Kawasaki
International Business Machines Corporation - Armonk NY
International Classification:
H01L 214763
US Classification:
438595
Abstract:
In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.

Method For Forming An Electronic Device

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US Patent:
6884672, Apr 26, 2005
Filed:
Nov 4, 2003
Appl. No.:
10/701191
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY, US
Serge Biesemans - Leuven, BE
Byeongju Park - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/8238
H01L021/336
US Classification:
438231, 438232, 438305
Abstract:
Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.

Reduction Of Gate-Induced Drain Leakage In Semiconductor Devices

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US Patent:
60906715, Jul 18, 2000
Filed:
Sep 30, 1997
Appl. No.:
8/941600
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY
Martin Gall - South Burlington VT
Jeffrey P. Gambino - Gaylorsville CT
Jack A. Mandelman - Stormville NY
Assignee:
Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
US Classification:
438291
Abstract:
Reduction of gate-induced-drain-leakage in metal oxide semiconductor (MOS) devices is achieved by performing an anneal in a non-oxidizing ambient. In one embodiment, the anneal is performed in a argon and/or ammonia ambients after gate sidewall oxidation that forms the spacers.

High Speed Gaas Mesfet Having Refractory Contacts And A Self-Aligned Cold Gate Fabrication Process

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US Patent:
48085456, Feb 28, 1989
Filed:
Apr 20, 1987
Appl. No.:
7/040014
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY
Robert R. Joseph - Poughkeepsie NY
Robert B. Renbeck - Staatsburg NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2131
US Classification:
437 41
Abstract:
Disclosed is a process fo fabrication of a MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide dummy gate mask consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide laeyr is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal.

Method Of Controlling Dopant Diffusion And Metal Contamination In Thin Polycide Gate Conductor Of Mosfet Device

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US Patent:
59239999, Jul 13, 1999
Filed:
Oct 29, 1996
Appl. No.:
8/741159
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY
Stephen Bruce Brodsky - Fishkill NY
Richard Anthony Conti - Mount Kisco NY
Badih El-Kareh - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 213205
H01L 214763
US Classification:
438592
Abstract:
A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Controlled Dopant Diffusion And Metal Contamination In Thin Polycide Gate Conductor Of Mosfet Device

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US Patent:
61147362, Sep 5, 2000
Filed:
Jul 12, 1999
Appl. No.:
9/351808
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY
Stephen Bruce Brodsky - Fishkill NY
Richard Anthony Conti - Mount Kisco NY
Badih El-Kareh - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
H01L 23283
US Classification:
257412
Abstract:
A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Process For Forming Planar Chip-Level Wiring

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US Patent:
46891137, Aug 25, 1987
Filed:
Mar 21, 1986
Appl. No.:
6/842576
Inventors:
Karanam Balasubramanyam - Hopewell Junction NY
Anthony J. Dally - Pleasant Valley NY
Jacob Riseman - Poughkeepsie NY
Seiki Ogura - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B44C 122
C23F 102
C03C 1500
B29C 3700
US Classification:
156643
Abstract:
Disclosed is a process of forming high density, planar, single- or multi-level wiring for a semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e. g. , metal) layer of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer.
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Karanam K Balasubramanyam from Hopewell Junction, NY, age ~82 Get Report