Search

Kamalesh N Ruparel

from Saratoga, CA
Age ~63
Get Report
Also known as:
Kirtida Te Ruparel, Kirtida K Ruparel, Natvarlal Rupa Kamalesh, Kamelesh Natvarlal
Phone and address:
20668 Seaton Ave, Saratoga, CA 95070
Related to:
Manjula Natvarlal Ruparel, 84Jitendr RuparelJitendra C Ghelani, 64Kirtida K Ruparel, 57Varsha C Ruparel, 48Nihal Ruparel, 32Vaishali S Gandhi, 46Jignesh Ruparel, 47Sandeep S Gandhi, 53Vaishali S Gandhi, 56Natvarlal J Ruparel, 95Swapna Vaidya Ruparel, 50
Connected to:
Chandrakant S Ruparelia, 68Komal D Ruparel, 34Kosha N Ruparel, 45Meena Ruparel, 64Nisha Ruparel, 69Matthew I Rupas, 34Prasanna D Rupasinghe, 62Andrey A Rupasov, 38Linda M Rupcich, 66Catherine L Rupcinski, 65

Kamalesh Ruparel Phones & Addresses

  • 20668 Seaton Ave, Saratoga, CA 95070
  • San Jose, CA
  • Cupertino, CA
  • Dallas, TX
  • Santa Clara, CA
  • Richardson, TX

Work

Company: Infinera Nov 2010 Position: Senior director

Education

Degree: MSCS School / High School: Southern Methodist University 1987 to 1990 Specialities: Computer Science

Skills

Semiconductors • Asic • Eda • Ic • Dft • Fpga • Product Management • Hardware Architecture • Soc • Product Marketing • Digital Signal Processors • Start Ups • Testing • Static Timing Analysis • Integration • Application Specific Integrated Circuits • Embedded Systems • Integrated Circuits • System on A Chip

Languages

Hindi • Gujarati

Interests

Emerging Technologies • Reading • Business Development Personal • Diversions • Philosophy • Music and Physical Fitness • Citizen

Emails

k***[email protected]

Industries

Semiconductors

Resumes

Resumes

Kamalesh Ruparel Photo 1

Kamalesh Ruparel

View page
Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Infinera since Nov 2010
Senior Director
Virage Logic, Inc. Jun 2007 - May 2010
Vice-President & GM, ASIP Solutions
Anchor Bay Technologies, Inc. Apr 2006 - Jan 2007
VP, Engineering
Cisco Systems, Inc. Oct 1996 - Mar 2006
Director, Engineering
Apple Computer Feb 1992 - Jul 1996
Senior Manager, VF & DFT Engineering
Education:
Southern Methodist University 1987 - 1990
MSCS, Computer Science The University of Texas at Austin 1983 - 1984
BSEE with Honors, Electrical Engineering
Skills:
Semiconductors
Asic
Eda
Ic
Dft
Fpga
Product Management
Hardware Architecture
Soc
Product Marketing
Digital Signal Processors
Start Ups
Testing
Static Timing Analysis
Integration
Application Specific Integrated Circuits
Embedded Systems
Integrated Circuits
System on A Chip
Interests:
Emerging Technologies
Reading
Business Development Personal
Diversions
Philosophy
Music and Physical Fitness
Citizen
Languages:
Hindi
Gujarati

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kamalesh Ruparel
Vice President
VIRAGE LOGIC INTERNATIONAL
Mfg Semiconductors/Related Devices · Software Development · Semiconductor and Related Device Manufacturing
700 E Middlefield Rd, Mountain View, CA 94043
47100 Bayside Pkwy, Fremont, CA 94538
(510) 360-8000, (510) 490-3841, (510) 743-8115, (510) 743-8119

Publications

Us Patents

Method And Apparatus For Transforming System Simulation Tests To Test Patterns For Ic Testers

View page
US Patent:
6363509, Mar 26, 2002
Filed:
Jan 16, 1996
Appl. No.:
08/590695
Inventors:
Ishwar Parulkar - Los Angeles CA
Kamalesh N. Ruparel - San Jose CA
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G01R 3128
US Classification:
714738, 714742
Abstract:
Techniques are disclosed for functionally testing integrated circuit chips for the particular design for which they are intended. The techniques operate to automatically and intelligently transform a test designed for verifying the design of a simulation model of an electronic system to test patterns for an isolated test on an Automatic Testing Equipment (ATE) system, of a particular integrated circuit chip within the simulation model.

Apparatus For Scannable D-Flip-Flop Which Scans Test Data Independent Of The System Clock

View page
US Patent:
56895178, Nov 18, 1997
Filed:
Jul 26, 1996
Appl. No.:
8/686506
Inventors:
Kamalesh Ruparel - San Jose CA
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G01R 3128
US Classification:
371 223
Abstract:
The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops.
Control profile
Kamalesh N Ruparel from Saratoga, CA, age ~63 Get Report