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Kalyan C Kankipati

from San Jose, CA
Age ~43
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Also known as:
Kaylan Kankipati
Phone and address:
3162 Fowler Rd, San Jose, CA 95135
(408) 204-9625
Related to:
Srihari R Vegesna, 53Srinivas R Vegesna, 55Raja Shaker Rao Jakilati, 53Jyothi Kankipati, 47
Connected to:
Sunder R Kankipati, 46Keith W Kankovsky, 59Mbaya Kankwenda, 79Mathiarasan Kanmadhian, 53Mehmet A Kanmaz, 35Jake M Kanmore, 66Adin J Kann, 34Angelia L Kann, 54Ben D Kann, 81Cheryl L Kann, 63

Kalyan Kankipati Phones & Addresses

  • 3162 Fowler Rd, San Jose, CA 95135 (408) 204-9625
  • Irvine, CA
  • Santa Clara, CA
  • Columbia, SC
  • 4206 Sophia Way, San Jose, CA 95134

Work

Company: Broadcom Nov 2018 Position: Master ic design engineer

Education

Degree: Master of Science, Masters School / High School: University of South Carolina 2001 to 2003 Specialities: Electrical Engineering

Skills

Asic • Soc • Simulations • Verilog • Integrated Circuit Design • Fpga • Semiconductors • Functional Verification • Systemverilog • Static Timing Analysis • Ic • Rtl Design • Vlsi • Eda • Application Specific Integrated Circuits • Testing • System on A Chip

Industries

Semiconductors

Resumes

Resumes

Kalyan Kankipati Photo 1

Master Ic Design Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Broadcom
Master Ic Design Engineer
Broadcom Aug 2013 - Oct 2018
Principal Ic Design Engineer
Broadcom Aug 2011 - Jul 2013
Senior Staff Ic Design Engineer
Altera Nov 2006 - Aug 2011
Member of Technical Staff
Nethra Imaging Jun 2005 - Nov 2006
Design Verification Engineer
Education:
University of South Carolina 2001 - 2003
Master of Science, Masters, Electrical Engineering Jawaharlal Nehru Technological University 1997 - 2001
Bachelors, Bachelor of Technology, Electronics Engineering
Skills:
Asic
Soc
Simulations
Verilog
Integrated Circuit Design
Fpga
Semiconductors
Functional Verification
Systemverilog
Static Timing Analysis
Ic
Rtl Design
Vlsi
Eda
Application Specific Integrated Circuits
Testing
System on A Chip

Publications

Us Patents

Transceiver System With Reduced Latency Uncertainty

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US Patent:
20090161738, Jun 25, 2009
Filed:
Sep 15, 2008
Appl. No.:
12/283652
Inventors:
Neville Carvalho - Campbell CA, US
Allan Thomas Davidson - San Jose CA, US
Andy Turudic - Hillsboro OR, US
Bruce B. Pedersen - Sunnyvale CA, US
David W. Mendel - Sunnyvale CA, US
Kalyan Kankipati - San Jose CA, US
Michael Menghui Zheng - Fremont CA, US
Seungmyon Park - Sunnyvale CA, US
Tim Tri Hoang - San Jose CA, US
Kumara Tharmalingam - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H04L 7/00
H04B 1/38
US Classification:
375219
Abstract:
A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Scalable Interconnect Modules With Flexible Channel Bonding

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US Patent:
20120027026, Feb 2, 2012
Filed:
Jul 28, 2010
Appl. No.:
12/845672
Inventors:
Keith Duwel - San Jose CA, US
Michael Menghui Zheng - Fremont CA, US
Vinson Chan - San Jose CA, US
Kalyan Kankipati - San Jose CA, US
International Classification:
H04J 3/16
US Classification:
370465
Abstract:
The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Scalable Interconnect Modules With Flexible Channel Bonding

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US Patent:
20140036931, Feb 6, 2014
Filed:
Jun 24, 2013
Appl. No.:
13/925284
Inventors:
Michael Menghui ZHENG - Fremont, US
Vinson CHAN - San Jose CA, US
Kalyan KANKIPATI - San Jose CA, US
International Classification:
H04J 3/16
US Classification:
370465
Abstract:
The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
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Kalyan C Kankipati from San Jose, CA, age ~43 Get Report