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Jovica Savic

from Downers Grove, IL

Jovica Savic Phones & Addresses

  • 4328 Roslyn Rd, Downers Grove, IL 60515 (630) 322-8792 (630) 512-0036
  • 500 Mansion Ct APT 312, Santa Clara, CA 95054 (630) 915-1391
  • Berwyn, IL
  • Rolling Meadows, IL
  • 500 Mansion Ct APT 312, Santa Clara, CA 95054 (630) 624-0220

Work

Position: Financial Professional

Education

Degree: Associate degree or higher

Emails

Publications

Us Patents

Method Of Manufacturing Photodefined Integral Capacitor With Self-Aligned Dielectric And Electrodes

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US Patent:
6349456, Feb 26, 2002
Filed:
Dec 31, 1998
Appl. No.:
09/224338
Inventors:
Gregory J. Dunn - Arlington Heights IL
Jovica Savic - Downers Grove IL
Allyson Beuhler - Downers Grove IL
Everett Simons - Palatine IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01G 700
US Classification:
29 2542, 29846, 29852, 216 17, 216 18, 3613011, 361303, 361313
Abstract:
A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

Multi-Layer Conductor-Dielectric Oxide Structure

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US Patent:
6541137, Apr 1, 2003
Filed:
Jul 31, 2000
Appl. No.:
09/629504
Inventors:
Angus Kingon - Cary NC
Gregory J. Dunn - Arlington Heights IL
Stephen Streiffer - Oak Park IL
Kevin Cheek - Raleigh NC
Jon-Paul Maria - Raleigh NC
Jovica Savic - Downers Grove IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
B32B 900
US Classification:
428701, 428702, 428699, 338226
Abstract:
A dielectric film is formed on a free-standing conductive metal layer to form a multi-layer foil comprising a conductive metal layer, a barrier layer and a dielectric oxide layer. Such multi-layer foils are mechanically flexible, and useful for the manufacture of capacitors. Examples of barrier layers include Ni—P or Ni—Cr alloys. After a second layer of conductive metal is deposited on a dielectric oxide surface opposing the first conductive metal layer, the resulting capacitor foil is processed into a capacitor. The resulting capacitor is a surface mounted capacitor or is formed as a integrated or embedded capacitor within a circuit board.

Multi-Layer Conductor-Dielectric Oxide Structure

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US Patent:
6841080, Jan 11, 2005
Filed:
Jan 28, 2003
Appl. No.:
10/352483
Inventors:
Angus Kingon - Cary NC, US
Gregory J. Dunn - Arlington Heights IL, US
Stephen Streiffer - Oak Park IL, US
Kevin Cheek - Raleigh NC, US
Jon-Paul Maria - Raleigh NC, US
Jovica Savic - Downers Grove IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01G 1300
H01G 400
H01G 500
H01G 700
H01G 900
US Classification:
216 6, 29 2503
Abstract:
A dielectric film is formed on a free-standing conductive metal layer to form a multi-layer foil comprising a conductive metal layer, a barrier layer and a dielectric oxide layer. Such multi-layer foils are mechanically flexible, and useful for the manufacture of capacitors. Examples of barrier layers include Ni—P or Ni—Cr alloys. After a second layer of conductive metal is deposited on a dielectric oxide surface opposing the first conductive metal layer, the resulting capacitor foil is processed into a capacitor. The resulting capacitor is a surface mounted capacitor or is formed as a integrated or embedded capacitor within a circuit board.

Polymer Thick Film Resistor, Layout Cell, And Method

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US Patent:
7038571, May 2, 2006
Filed:
May 30, 2003
Appl. No.:
10/448993
Inventors:
Gregory J. Dunn - Arlington Heights IL, US
Jovica Savic - Downers Grove IL, US
Remy J. Chelini - Crystal Lake IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01C 1/012
US Classification:
338307, 338295
Abstract:
A printed circuit polymer thick film (PTF) resistor includes tolerance control material that substantially surrounds the resistor body and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment, the tolerance control material is the same metallic material as the printed circuit conductors, and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad of the resistor. A layout cell is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

Printed Circuit Embedded Capacitors

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US Patent:
7056800, Jun 6, 2006
Filed:
Dec 15, 2003
Appl. No.:
10/736327
Inventors:
Robert T. Croswell - Hanover Park IL, US
Gregory J. Dunn - Arlington Heights IL, US
Robert B. Lempkowski - Elk Grove IL, US
Aroon V. Tungare - Winfield IL, US
Jovica Savic - Downers Grove IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21/20
H01G 4/00
US Classification:
438381, 3613011
Abstract:
One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode () overlaying a first substrate layer () of the printed circuit structure, a crystallized dielectric oxide core () overlaying the first electrode, a second electrode () overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer () disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Dielectric Sheet, Method For Fabricating The Dielectric Sheet, Printed Circuit And Patch Antenna Using The Dielectric Sheet, And Method For Fabricating The Printed Circuit

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US Patent:
7079373, Jul 18, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/837461
Inventors:
Gregory J. Dunn - Arlington Heights IL, US
Jeffrey M. Petsinger - Wayne IL, US
Jovica Savic - Downers Grove IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01G 4/06
H05K 1/11
US Classification:
361311, 361793, 3613212
Abstract:
A dielectric sheet () includes a photodielectric support layer () that may be glass reinforced and a dielectric laminate (). The dielectric laminate includes first and second metal foil layers (), and a dielectric layer () disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

Two-Layer Patterned Resistor

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US Patent:
7105913, Sep 12, 2006
Filed:
Dec 22, 2003
Appl. No.:
10/743589
Inventors:
Gregory J. Dunn - Arlington Heights IL, US
Scott N. Carney - Palatine IL, US
Jovica Savic - Downers Grove IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 27/082
US Classification:
257582
Abstract:
A technique for fabricating a patterned resistor on a substrate produces a patterned resistor () including two conductive end terminations () on the substrate, a pattern of first resistive material () having a first width () and a first sheet resistance, and a pattern of second resistive material () having a second width () and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed.

Printed Circuit Patterned Embedded Capacitance Layer

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US Patent:
7138068, Nov 21, 2006
Filed:
Mar 21, 2005
Appl. No.:
11/084938
Inventors:
Gregory J. Dunn - Arlington Heights IL, US
Robert T. Croswell - Hanover Park IL, US
Jaroslaw A. Magera - Palatine IL, US
Jovica Savic - Downers Grove IL, US
Aroon V. Tungare - Winfield IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21/302
US Classification:
216 83, 257773, 438381, 438778, 438793, 438794, 438791
Abstract:
A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating () a ceramic oxide layer () overlying a conductive metal layer () overlying a printed circuit substrate (), perforating () the ceramic oxide layer within a region (), and removing () the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
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