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Joseph Andrew Cetin

from La Jolla, CA
Age ~51
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Also known as:
Joseph A Cetin, Yusuf Cetin
Related to:
Fatma CetinChristin CetinNebahat CetinAyse CetinTao Moua
Connected to:
Adam Cetin, 35Asude Cetin, 51Aykut Cetin, 58Bedri C Cetin, 59Bonnie L Cetin, 64Gretchen L Cetin, 80Gulsah Cetin, 42Robert J Cetin, 62Andrea L Cetina, 36Erica A Cetina, 37

Joseph Cetin Phones & Addresses

  • La Jolla, CA
  • 12885 Starwood Ln, San Diego, CA 92131
  • Encinitas, CA
  • Palo Alto, CA
  • Sanger, CA
  • Daytona Beach, FL
  • 1213 Orchard Glen Cir, Encinitas, CA 92024

Work

Position: Protective Service Occupations

Education

Degree: Associate degree or higher

Skills

Mixed Signal • Analog • Analog Circuit Design • Semiconductors • Capa • Medical Devices • Design Control • Concurrent Engineering • Risk Management • Quality Systems Design • Fmea • Iso 14971 • Iso 13485 • Wireless • Usb • Pcie • Serdes • Ic • Cmos • Asic • Power Management • Integrated Circuit Design • Silicon • Soc • Iec 60601

Industries

Medical Devices

Resumes

Resumes

Joseph Cetin Photo 1

Joseph Cetin

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Location:
San Diego, CA
Industry:
Medical Devices
Skills:
Mixed Signal
Analog
Analog Circuit Design
Semiconductors
Capa
Medical Devices
Design Control
Concurrent Engineering
Risk Management
Quality Systems Design
Fmea
Iso 14971
Iso 13485
Wireless
Usb
Pcie
Serdes
Ic
Cmos
Asic
Power Management
Integrated Circuit Design
Silicon
Soc
Iec 60601

Business Records

Name / Title
Company / Classification
Phones & Addresses
Joseph A. Cetin
President
NUMERICOMM, INC
School/Educational Services
9974 Scripps Rnch Blvd, San Diego, CA 92131
(858) 735-1919

Publications

Us Patents

Universal Serial Bus (Usb) Driver Circuit, System, And Method

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US Patent:
7595674, Sep 29, 2009
Filed:
Apr 25, 2006
Appl. No.:
11/380127
Inventors:
Joseph A. Cetin - San Diego CA, US
Jason F. Muriby - San Diego CA, US
Matthew D. Sienko - La Jolla CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 5/12
US Classification:
327170, 327108, 326 82
Abstract:
A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1. 5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate. Therefore, the driver circuit, system, and method avoids passive electrical components and the PVT fluctuations associated therewith.

Analog-To-Digital Converter Circuit And Method With Programmable Resolution

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US Patent:
7642943, Jan 5, 2010
Filed:
Dec 21, 2007
Appl. No.:
11/963314
Inventors:
Joseph Cetin - San Diego CA, US
Jason Muriby - San Diego CA, US
Matthew Sienko - La Jolla CA, US
Ibrahim Yayla - Delmar CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03M 1/12
US Classification:
341156, 323272
Abstract:
Disclosed are a circuit and a method for an analog-to-digital conversion with programmable resolution. The circuit includes a resistor ladder comprising a plurality of resistors coupled to a plurality of comparators; wherein the resistor ladder is further coupled to a switch logic circuit and a plurality of current sources; and wherein the switch logic circuit is configured to control an operation of a plurality of switches to alter conversion resolution of the ADC, and an error correction circuit coupled to the outputs of the plurality of comparators, wherein the ADC is configured to perform a first conversion step and a second conversion step, and wherein the ADC is configured to perform only the first conversion step when programmed for lower conversion accuracy and higher conversion speed.

Differential Crystal Oscillator Circuit With Peak Regulation

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US Patent:
7683730, Mar 23, 2010
Filed:
Sep 20, 2005
Appl. No.:
11/230587
Inventors:
Joseph Andrew Cetin - San Diego CA, US
Jason Faris Muriby - San Diego CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L 1/00
US Classification:
331186, 331158, 331183
Abstract:
A clock circuit has a crystal. A differential amplifier has a first input coupled to a first node of the crystal and a second input of the differential amplifier coupled to a bias signal and an output of the differential amplifier coupled to a second node of the crystal.

Linearized Digital Phase-Locked Loop Method For Maintaining End Of Packet Time Linearity

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US Patent:
7826581, Nov 2, 2010
Filed:
Oct 5, 2004
Appl. No.:
10/959259
Inventors:
Stephen M. Prather - Austin TX, US
Matthew S. Berzins - Austin TX, US
Charles A. Cornell - Austin TX, US
Steven P. Larky - Del Mar CA, US
Joseph A. Cetin - San Diego CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03D 3/24
US Classification:
375373, 375376
Abstract:
An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

Operational Amplifier And Method For Amplifying A Signal With Shared Compensation Components

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US Patent:
7884672, Feb 8, 2011
Filed:
Nov 1, 2006
Appl. No.:
11/592075
Inventors:
Joseph A. Cetin - San Diego CA, US
Matthew D. Sienko - La Jolla CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03F 3/45
US Classification:
330258, 330254, 330260, 330271, 330264
Abstract:
An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.

Method And Circuit For Improving Device Power Up Timing And Predictability

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US Patent:
20050213268, Sep 29, 2005
Filed:
Mar 22, 2005
Appl. No.:
11/088029
Inventors:
Joseph Cetin - San Diego CA, US
Nathan Moyal - West Linn OR, US
International Classification:
H02H007/00
US Classification:
361018000
Abstract:
Method and system for controllably and sequentially powering up subsystems of an electronic system, device or integrated circuit. In one example, a first supply voltage is selectively applied to a first subsystem, and when the first supply voltage has reached a predetermined value, a second supply voltage is selectively applied to the second subsystem. The first and second supply voltages may also be boosted to provide fast startup timing. In this manner, the first subsystem is powered-up before the second supply voltage is applied to the second subsystem—this provides for controlled, sequential power up of the subsystems of the electronic system, device or integrated circuit.

Digitally Controlled Dynamic Power Management Unit For Uninterruptible Power Supply

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US Patent:
20090172425, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
12/006229
Inventors:
Joseph A. Cetin - San Diego CA, US
Patrick J. Sullivan - San Diego CA, US
Assignee:
Simtek - Colorado Springs CO
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A memory system power management process includes providing a first level of power to operate a memory system while a primary power source is enabled, detecting an interruption of the primary power source, increasing a frequency of an oscillator driving a charge pump of a power converter providing the first level of power, and beginning a memory operation that increases a load on the power converter.

Amplifier Circuit With Bias Stage For Controlling A Common Mode Output Voltage Of The Gain Stage During Device Power-Up

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US Patent:
7560987, Jul 14, 2009
Filed:
May 30, 2006
Appl. No.:
11/420948
Inventors:
Joseph A. Cetin - San Diego CA, US
Matthew D. Sienko - La Jolla CA, US
Jason F. Muriby - San Diego CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03F 3/45
US Classification:
330258
Abstract:
An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.
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Joseph Andrew Cetin from La Jolla, CA, age ~51 Get Report