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Jorge Adrian Kittl

from Austin, TX
Age ~63
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Also known as:
Jorge A Kittl, Jorge Adriann Kittl, Jorge Adrian Kitti, Jorge Adrian Ktt, Jorge A Kitti, Jorge Kittil
Related to:
Julian Jorge KittlAna Kittl, 36Maria KittlMaria A Kittl, 62
Connected to:
Erich Kittlaus, 42Barbara A Kittle, 78Beverley A Kittle, 68Brad E Kittle, 74Brett A Kittle, 64Bruce M Kittle, 84Christopher J Kittle, 40Danny L Kittle, 70Diann H Kittle, 48Dustin J Kittle, 43

Jorge Kittl Phones & Addresses

  • Austin, TX
  • San Antonio, TX
  • Converse, TX
  • Boerne, TX
  • Garland, TX
  • Plano, TX
  • Round Rock, TX
  • Dallas, TX

Work

Company: Samsung Feb 2013 Position: Vice president

Education

Degree: Master of Business Administration, Masters School / High School: The University of Texas at Austin 2012 to 2014

Skills

Thin Films • Characterization • R&D • Materials Science • Semiconductors • Cmos • Physics • Nanotechnology • Manufacturing • Ic • Semiconductor Industry • Nanofabrication • Photolithography • Silicon • Simulations

Industries

Semiconductors

Resumes

Resumes

Jorge Kittl Photo 1

Vice President

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Samsung
Vice President
Imec 2007 - 2012
Chief Scientist
Ku Leuven 2007 - 2012
Professor, Department of Physics and Astronomy
Texas Instruments 1997 - 2007
Distinguished Member Technical Staff, Senior Member Technical Staff
Texas Instruments 2001 - 2007
On Site Manager at Imec, Ti Assignee at Imec
Education:
The University of Texas at Austin 2012 - 2014
Master of Business Administration, Masters The University of Texas at Austin 1999 - 2001
Master of Business Administration, Masters, Business Harvard University 1991 - 1993
Caltech 1987 - 1991
Doctorates, Doctor of Philosophy, Applied Physics Caltech 1986 - 1987
Master of Science, Masters, Applied Physics University of Buenos Aires 1985 - 1985
Skills:
Thin Films
Characterization
R&D
Materials Science
Semiconductors
Cmos
Physics
Nanotechnology
Manufacturing
Ic
Semiconductor Industry
Nanofabrication
Photolithography
Silicon
Simulations

Publications

Us Patents

Method Of Forming A Silicide Layer Using Metallic Impurities And Pre-Amorphization

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US Patent:
6372566, Apr 16, 2002
Filed:
Jul 2, 1998
Appl. No.:
09/110034
Inventors:
Jorge A. Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 218238
US Classification:
438206, 438158, 438162, 438528, 438532, 438533, 438659
Abstract:
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.

Method To Enhance The Formation Of Nucleation Sites On Silicon Structures And An Improved Silicon Structure

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US Patent:
6429455, Aug 6, 2002
Filed:
Sep 16, 1999
Appl. No.:
09/397462
Inventors:
Vincent Maurice McNeil - Dallas TX
Jorge Adrian Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2904
US Classification:
257 49, 257763, 257764, 257770, 257384, 257388, 257412, 438583, 438649, 438655, 438685, 438683
Abstract:
A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region ( ): masking the at least one narrow silicon structure ( ) with a mask ( ); treating the at least one nucleation region ( ) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure ( ). In another embodiment, a silicon device capable of undergoing a phase transformation comprises at least one narrow silicon structure ( ) formed of TiSi ; and at least one nucleation region ( ) attached to the at least one narrow silicon region ( ), said at least one nucleation region ( ) having a width which is greater than a width of said at least one narrow silicon structure ( ) and said at least one nucleation region ( ) capable of generating a high density of C54 nucleation sites such that said high density of nucleation sites causes a phase transformation ( ) to propagate along the at least one silicon structure ( ).

Method To Improve Silicide Formation On Polysilicon

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US Patent:
6777300, Aug 17, 2004
Filed:
Dec 19, 2001
Appl. No.:
10/023825
Inventors:
Jorge Adrian Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21336
US Classification:
438305, 438303
Abstract:
A polysilicon layer of a gate structure is covered by an implant blocking layer (e. g. , silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e. g. , for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Preferential Lateral Silicidation Of Gate With Low Source And Drain Silicon Consumption

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US Patent:
60461055, Apr 4, 2000
Filed:
Apr 15, 1998
Appl. No.:
9/060970
Inventors:
Jorge Adrian Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2128
US Classification:
438655
Abstract:
Method of forming a salicide on a gate structure uses sidewall spacers which leave at least 30 percent of the gate sidewall exposed. After metal deposition, which has at least 50 percent step coverage, an anisotropic etch removes some or all of the metal on horizontal surfaces. Silicides formed from this metal layer are conformal, or even thicker on the sides of the gate than on horizontal structures. This achieves low sheet resistance on the gate, while remaining compatible with shallow junctions.

Method Of Forming A Silicide Layer Using An Angled Pre-Amorphization Implant

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US Patent:
62041320, Mar 20, 2001
Filed:
May 6, 1999
Appl. No.:
9/306494
Inventors:
Jorge A. Kittl - Plano TX
Christopher Bowles - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21336
US Classification:
438299
Abstract:
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane, the method comprising the steps of: forming a semiconductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); amorphizing a portion of the conductive structure by introducing an amorphizing substance into the semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate (step 310 of FIG. 3); forming a metal layer on the conductive structure (step 312 of FIG. 3); and wherein the metal layer interacts with the semiconductive structure in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure (step 314 of FIG. 3). Preferably, the semiconductive structure is comprised of a material selected from the group consisting of: doped polysilicon, undoped polysilicon, epitaxial silicon, and any combination thereof; and the metal layer is comprised of a material selected from the group consisting of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.

Method Of Forming A Silicide Layer Using A Pre-Amorphization Implant Which Is Blocked From Source/Drain Regions By A Layer Of Photoresist

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US Patent:
63262894, Dec 4, 2001
Filed:
Aug 23, 1999
Appl. No.:
9/378824
Inventors:
Mark S. Rodder - University Park TX
Jorge A. Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 214763
US Classification:
438592
Abstract:
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate (step 102 of FIG. 1); forming a source/drain regions and a channel region in the semiconductor substrate (step 108), the channel region situated between the source/drain regions and under the gate structure; forming a photoresist layer over the source/drain regions (step 110); amorphizing a portion of the gate structure by introducing an amorphizing substance into the gate structure (step 112); removing the photoresist layer after the step of amorphizing a portion of the gate structure step 114); forming a metal layer on the conductive structure, the metal layer interacts with the gate structure in the amorphized portion of the gate structure and the source/drain regions so as to form a lower resistivity silicide on the gate structure and the source/drain regions (step 116); and wherein the photoresist layer blocks the amorphizing substance from the source/drain regions and allows the amorphizing substance to enter the gate structure.

Transistor Having An Improved Salicided Gate And Method Of Construction

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US Patent:
60487844, Apr 11, 2000
Filed:
Dec 15, 1998
Appl. No.:
9/212189
Inventors:
Jorge A. Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 213205
H01L 21336
H01L 21477
US Classification:
438592
Abstract:
A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Implant Enhancement Of Titanium Silicidation

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US Patent:
60048719, Dec 21, 1999
Filed:
Jun 3, 1997
Appl. No.:
8/868173
Inventors:
Jorge Adrian Kittl - Plano TX
Keith A. Joyner - Richardson TX
George R. Misium - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 213205
H01L 214763
US Classification:
438592
Abstract:
A method of forming silicided narrow (i. e. , sub-0. 25. mu. m) polysilicon lines. A layer of titanium is deposited over a semiconductor body having polysilicon lines formed thereon Either before or after the titanium deposition and before the react step, an implant is performed using a gas that will not poison the subsequent silicidation reaction. Exemplary gases include the noble element gases such as argon, krypton, xenon, and neon. The titanium is then reacted with the polysilicon lines to form titanium silicide. The gas implant causes the C49 grain size of the titanium silicide to be reduced, which makes the transformation to the C54 phase easier. Finally, an anneal is performed to transform the titanium silicide from the C49 phase to the C54 phase.
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Jorge Adrian Kittl from Austin, TX, age ~63 Get Report