Jongrit Lerdworatawee

20080136692, Jun 12, 2008

Dec 12, 2006

11/637643

Jongrit Lerdworatawee - Austin TX, US
Mehmet Fatih Erden - Pittsburgh PA, US

Seagate Technology LLC - Scotts Valley CA

H03M 3/04
H03M 1/40

341143, 341155

A method of reading data is provided. The method includes receiving an analog signal, converting the analog signal to a one bit wide digital signal at a first sampling frequency, and downsampling the digital signal to provide the one bit wide digital signal at a second sampling frequency. The method further includes conditioning the digital signal prior to providing the digital signal to the detector. The conditioning can be performed after downsampling the digital signal. A data communication channel is also provided. The data communication channel includes an analog to digital converter configured to provide a first one bit wide digital data stream at a first sampling frequency and a signal conditioning member configured to accept the first one bit wide digital data stream at a first sampling frequency and provide a second one bit wide digital data stream at a second sampling frequency.

20190305683, Oct 3, 2019

Mar 28, 2018

15/937947

- San Diego CA, US
Jongrit LERDWORATAWEE - San Diego CA, US
Yu PU - San Diego CA, US

H02M 3/158
G05F 1/26

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

20190089364, Mar 21, 2019

Sep 15, 2017

15/706449

- San Diego CA, US
Jongrit Lerdworatawee - Santee CA, US
Chunlei Shi - San Diego CA, US

H03L 7/187
H03L 7/07
H03L 7/197
H03L 7/099
H02M 3/335
G01R 31/317

A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

20180034417, Feb 1, 2018

Jul 7, 2017

15/644443

- San Diego CA, US
Jongrit LERDWORATAWEE - Santee CA, US
Song SHI - San Diego CA, US
Thomas MARRA - San Diego CA, US

H03F 1/02
H03F 3/19
H02M 3/156
G05F 1/46
H03F 3/21
H02M 1/08

Certain aspects of the present disclosure provide methods and apparatus for adjusting voltage regulators of a power supply, such as an envelope tracking power supply. Certain aspects provide a power supply. The power supply may include a first voltage regulator having an output coupled to a voltage supply node of an amplifier. The power supply may further include a second voltage regulator having an output coupled to the voltage supply node of the amplifier. The power supply may further include a controller for adjusting a ratio of an average current supplied by the first voltage regulator to an average current supplied by the second voltage regulator to the voltage supply node of the amplifier based on an output voltage supplied to the voltage supply node of the amplifier by the first voltage regulator and the second voltage regulator.

20160254746, Sep 1, 2016

Feb 27, 2015

14/634412

- San Diego CA, US
Jongrit Lerdworatawee - Santee CA, US

H02M 3/158
H03F 3/21

The present disclosure includes multi-level switching regulator circuits and methods with finite state machine control. In one embodiment, a circuit comprises a switching regulator and a finite state machine. The switching regulator comprises high side and low side switches, and at least one capacitor. A finite state machine receiving a switching signal and a duty cycle signal to generate switch control signals to the switches. The switches are turned on and off under control of the finite state machine in response to transitions of the switching signal and the duty cycle signal. The switching signal may be generated from an envelope tracking signal, and the switching regulator may be part of an envelope tracking system.