Search

John A Klashka

from Hudson, MA
Age ~82
Get Report
Also known as:
John Living Klashka, John Klashka Lt
Related to:
Chris J Klashka, 53Anna Klashka, 49
Connected to:
Karen A Klasic, 64David W Klasing, 61Michael P Klasing, 45Patricia L Klasinski, 68Scott A Klasinski, 55Brent M Klaske, 55Stephen B Klaske, 54Howard N Klaskin, 61Mary A Klasko, 63Neil B Klasky, 58

John Klashka Phones & Addresses

  • Hudson, MA
  • Littleton, MA
  • 42 Highwood Way, North Andover, MA 01845 (978) 685-0307
  • 42 Highwood Way, North Andover, MA 01845 (978) 771-3123

Work

Company: Dell emc 1992 to 2006 Position: Retired

Education

Degree: Bachelors, Bachelor of Science School / High School: Northeastern University 1960 to 1964 Specialities: Electronics Engineering

Skills

Program Management • Project Management • Management • Strategic Planning • Process Improvement • Public Speaking • Team Building • Microsoft Office • Customer Service • Strategy • Training

Interests

Kids • Cooking • Exercise • Electronics • Traveling • Nascar • Sweepstakes • Home Improvement • International Traavel • Reading • Crafts • Gourmet Cooking • Sports • Travel • Collecting • Home Decoration

Emails

k***[email protected]

Industries

Philanthropy

Resumes

Resumes

John Klashka Photo 1

John Klashka

View page
Location:
42 Highwood Way, North Andover, MA 01845
Industry:
Philanthropy
Work:
Dell Emc 1992 - 2006
Retired
Education:
Northeastern University 1960 - 1964
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Program Management
Project Management
Management
Strategic Planning
Process Improvement
Public Speaking
Team Building
Microsoft Office
Customer Service
Strategy
Training
Interests:
Kids
Cooking
Exercise
Electronics
Traveling
Nascar
Sweepstakes
Home Improvement
International Traavel
Reading
Crafts
Gourmet Cooking
Sports
Travel
Collecting
Home Decoration

Publications

Us Patents

Data Reduction Using Rank-Of-Ranks Methodology

View page
US Patent:
6385762, May 7, 2002
Filed:
Jun 21, 1999
Appl. No.:
09/337361
Inventors:
Santi B. Lahiri - Winchester MA
John A. Klashka - North Andover MA
David Marshall Fredericksen - Hudson NH
Walter D. Shine - Salisbury MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1750
US Classification:
716 10
Abstract:
Data reduction for testing results obtained from the diagnostic testing of signal integrity at node points along a PC board using a Rank-of-Ranks data analysis methodology. The Rank-of-Ranks methodology including a reduction of node points along the PC board by the application of a node point reduction algorithm. Calculating a ratio of the Standard Deviation by the Mean for each node point and for each testing parameter to arrive at a Coefficient of Variation. Each node point is sorted and ranked based on the Coefficient of Variation for each tested parameter at a time. At each node point, Rank values of all the parameters are summed and then sorted on the basis of the Rank values. The node points are Re-ranked based on the sorted Rank values. The Re-ranked node points are entered into an ordered list or matrix where critical node points are chosen from the top of the Re-ranked node points for study, re-design and/or further testing of the PC board.

Multiple Dma Controller Chip Sequencer

View page
US Patent:
48315230, May 16, 1989
Filed:
Aug 31, 1988
Appl. No.:
7/239074
Inventors:
Richard P. Lewis - Sandown NH
John A. Klashka - North Andover MA
Assignee:
BULL HN Information Systems Inc. - Billerica MA
International Classification:
G06F 1322
G06F 1300
US Classification:
364200
Abstract:
A universal peripheral controller is disclosed which uses DMA devices to provide access between a plurality of peripheral devices and other circuits within a computer system. A processor in the computer system recognizes a request from the controller to connect a peripheral via the system bus to another circuit connected thereto and establishes the connection. The processor then passes information to the controller and leaves the task of controlling the transfer of information to the DMA circuitry in the controller. The controller has a sequencer which examines each of the plurality of peripherals connected to it in a round robin operation to determine which peripherals are requesting a connection via the computer system bus to transfer information. The sequencer limits the time each peripheral can be connected to the system bus before servicing another peripheral request in order that all peripherals have equal access to the system bus.

Bus Activity Sequence Controller

View page
US Patent:
48962660, Jan 23, 1990
Filed:
Jun 3, 1987
Appl. No.:
7/057460
Inventors:
John A. Klashka - North Andover MA
Sidney L. Kaufman - Stoughton MA
Krzysztof A. Kowal - Framingham MA
Richard P. Lewis - Sandown NH
John L. McNamara - Tweksbury MA
Assignee:
Bull HN Information Systems Inc. - Billerica MA
International Classification:
G06F 1332
US Classification:
364200
Abstract:
The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Universal Peripheral Controller Self-Configuring Bootloadable Ramware

View page
US Patent:
48036234, Feb 7, 1989
Filed:
Oct 31, 1986
Appl. No.:
6/925431
Inventors:
John A. Klashka - North Andover MA
Sidney L. Kaufman - Stoughton MA
Krzysztof A. Kowal - Framingham MA
Richard P. Lewis - Sandown NH
Susan L. Raisbeck - Chelmsford MA
John L. McNamara - Tewksbury MA
Assignee:
Honeywell Bull Inc. - Minneapolis MN
International Classification:
G06F 1310
US Classification:
364200
Abstract:
In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e. g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc. ) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.
Control profile
John A Klashka from Hudson, MA, age ~82 Get Report