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John Frissell Phones & Addresses

  • 15 Horseshoe Rd, Dracut, MA 01826 (978) 453-0755
  • 5 Horseshoe Rd, Dracut, MA 01826 (978) 453-0755
  • Swansea, MA
  • 31 Cove St #1, Swansea, MA 02777 (978) 453-0755

Professional Records

License Records

John M Frissell

Address:
Dracut, MA 01826
License #:
85887 - Expired
Issued Date:
Aug 1, 1973
Expiration Date:
Mar 11, 1981
Type:
Broker

Publications

Us Patents

Multiple Clock Selection System

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US Patent:
4229699, Oct 21, 1980
Filed:
May 22, 1978
Appl. No.:
5/908115
Inventors:
John M. Frissell - Dracut MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
H03K 117
US Classification:
328 63
Abstract:
A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.

Controller Device With Diagnostic Capability For Use In Interfacing A Central Processing Unit With A Peripheral Storage Device

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US Patent:
4327408, Apr 27, 1982
Filed:
Apr 17, 1979
Appl. No.:
6/030727
Inventors:
John M. Frissell - Dracut MA
Kris E. Swanson - Grafton MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 300
US Classification:
364200
Abstract:
A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate. During a normal read operation, read signals are sent from the peripheral storage device to the sequencer through the multiplexer and then from the sequencer to the CPU through the buffer. During a test write operation, the input to the peripheral storage device is disabled and write signals that would normally be sent from the sequencer to the peripheral storage device are sent to the microprocessor and then from the microprocessor to the CPU.

Data Transfer Technique For Use With Peripheral Storage Devices

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US Patent:
4228501, Oct 14, 1980
Filed:
Jun 21, 1978
Appl. No.:
5/917631
Inventors:
John M. Frissell - Dracut MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 1304
US Classification:
364200
Abstract:
Data processing apparatus wherein circuitry for data transfer between a central processor unit (CPU) and a peripheral storage unit, such as a hard disk storage unit, comprises a data transfer bus by which a block of data words being transferred is supplied to a temporary storage unit capable of storing the entire block. Means are provided to prevent any data transfer between the data bus and the CPU interface unit while the block of data words is transferred between the temporary storage unit and the peripheral storage unit and to permit transfer between the CPU interface unit and the bus when data is not being transferred between the temporary storage unit and the peripheral storage unit.

Seek Multitasking Disk Controller

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US Patent:
4935828, Jun 19, 1990
Filed:
Jun 30, 1988
Appl. No.:
7/213430
Inventors:
John M. Frissell - Dracut MA
Assignee:
Wang Laboratories, Inc. - Lowell MA
International Classification:
G11B 2108
G06F 1300
US Classification:
360 7804
Abstract:
A method and apparatus for increasing the performance of disk drive access by delaying a pending data transfer operation to an individual disk drive until immediately before the start of the target sector so as to allow servicing of an intervening seek operation to another disk drive.
John M Frissell from Dracut, MA, age ~72 Get Report