Josephus Christianus Ebergen

6420907, Jul 16, 2002

Sep 29, 2000

09/676430

Ivan E. Sutherland - Santa Monica CA
Scott M. Fairbanks - Mountain View CA
Josephus C. Ebergen - San Francisco CA

Sun Microsystems, Inc. - Palo Alto CA

H03K 19094

326121, 326 93, 326 95, 326119

One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conductor that is configured to drive the first conductor to a first voltage level to indicate a first state. The system also includes a second drive circuit coupled to the first conductor that is configured to drive the first conductor to a second voltage level to indicate a second state. The system additionally includes a condition input that indicates a condition. The system is configured so that the first drive circuit drives the first conductor to the first voltage level based upon the condition indicated by the condition input. In one embodiment of the present invention, the first drive circuit is additionally configured to drive the first conductor to the first voltage level based upon the state indicated by the voltage carried on the first conductor. In one embodiment of the present invention, the system additionally includes a keeper circuit coupled to the first conductor that is configured to hold the voltage on the first conductor at a stable value, unless the voltage is changed by a drive circuit.

6486709, Nov 26, 2002

May 11, 2001

09/854094

Ivan E. Sutherland - Santa Monica CA
Josephus C. Ebergen - San Francisco CA

Sun Microsystems, Inc. - Santa Clara CA

H03K 1920

326121, 326 93, 326112, 326119

One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit. Upon receiving a data item to be distributed, the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item. For each destination that is free to receive the data item, the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.

6486721, Nov 26, 2002

Mar 2, 2001

09/798662

Mark R. Greenstreet - Vancouver, CA
Josephus C. Ebergen - San Francisco CA

Sun Microsystems, Inc. - Santa Clara CA

H03K 3356

327211, 327213

A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.

6629301, Sep 30, 2003

Sep 15, 2000

09/663456

Ivan Sutherland - Santa Monica CA
Josephus Ebergen - San Francisco CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1750

716 8, 716 1

An apparatus and method for finding suitable transistor sizes for complex logic networks. An electrical âlogical effort modelâ of a logic circuit is made by replacing each logic element with a simple electrical model and retaining the wiring topology of the original circuit. The logical effort model is a DC circuit with parameters that depending only on the gain chosen for the logic elements in the critical path, the stray capacitance of critical connections, and the logical effort of each logic element. A circuit simulation of the logical effort model produces voltages proportional to desired transistor widths. In working on the electrical model, the circuit simulator merely solves the set of simultaneous equations implied by the model. Alternate methods are also described.

6700825, Mar 2, 2004

Sep 29, 2000

09/677442

Josephus C. Ebergen - San Francisco CA

Sun Microsystems, Inc. - Santa Clara CA

G11C 700

365221, 365239

A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermined protocol of cell transfers, in the same order as received. Transfer rules or protocol are controlled by a control circuit implemented using asynchronous pipeline modules or a control circuit relying upon transition signaling.

6707317, Mar 16, 2004

Apr 29, 2002

10/135166

Josephus C. Ebergen - San Francisco CA
Ivan E. Sutherland - Santa Monica CA
Jon Lexau - Beaverton OR
Jonathan Gainsley - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

H03K 19096

326 95, 326 83, 326112

One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage.

6772243, Aug 3, 2004

Dec 19, 2000

09/742162

Ian W. Jones - Palo Alto CA
Josephus C. Ebergen - San Francisco CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 300

710 57, 710 52, 710 56, 711170, 709234

Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to ânâ stages of the FIFO and configured to output a partial fullness indicator signal based on the full/empty states of the stages coupled to the m-out-of-n detector. The m-out-of-n detector may be configured to output the partial fullness indicator signal in a first state when âmâ stages coupled to the m-out-of-n detector are full, and to output the partial fullness indicator signal in a second state when âmâ stages coupled to the m-out-of-n detector are empty. The number of full stages of the FIFO lies in a first range when the m-out-of-n detector outputs the signal in the first state, and in a second range when the m-out-of-n detector outputs the signal in the second state. The bounds for the ranges may be determined based on factors such as the input and output rate characteristics of the FIFO.

6892278, May 10, 2005

Mar 5, 2002

10/091994

Josephus C. Ebergen - San Francisco CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F012/00
G06F012/08

711118, 711165, 711132

One embodiment of the present invention provides a system that implements a last-in first-out buffer. The system includes a plurality of cells arranged in a linear array to form the last-in first-out buffer, wherein a given cell in the interior of the linear array is configured to receive get and put calls from a preceding cell in the linear array, and to make get and put calls to a subsequent cell in the linear array. If the given cell contains no data items, the given cell is configured to make a get call to retrieve a data item from the subsequent cell. In this way the data item becomes available in the given cell to immediately satisfy a subsequent get call to the given cell without having to wait for the data item to propagate to the given cell from subsequent cells in the linear array. If the given cell contains no space for additional data items, the given cell is configured to make a put call to transfer a data item to the subsequent cell. In this way, space becomes available in the given cell to immediately satisfy a subsequent put call to the given cell without having to wait for data in the given cell to propagate to subsequent cells in the linear array.