Jeffrey D Bude

6528845, Mar 4, 2003

Jul 14, 2000

09/616569

Jeffrey D. Bude - New Providence NJ
Richard J. McPartland - Nazareth PA
Ranbir Singh - Orlando FL

Lucent Technologies Inc. - Murray Hill NJ

H01L 29792

257324

The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

6531751, Mar 11, 2003

Mar 17, 1999

09/271084

David Abusch-Magder - Maplewood NJ
Jeffrey Devin Bude - New Providence NJ

Agere Systems Inc. - Allentown PA

H01L 2976

257412, 257 77, 257316

A semiconductor device in which hole-induced damage to the dielectric layer is reduced is disclosed. In the device, a layer of a conductive, high bandgap (i. e. a material with a bandgap greater than 1. 1 eV) material is formed adjacent to the dielectric layer. The presence of the high bandgap material reduces the hole-induced damage to the dielectric layer that occurs during device operation compared to devices in which the conductive material adjacent to the dielectric is silicon.

7012314, Mar 14, 2006

Jun 3, 2003

10/453037

Jeffrey Devin Bude - New Providence NJ, US
Malcolm Carroll - Cranford NJ, US
Clifford Alan King - New York City NY, US

Agere Systems Inc. - Allentown PA

H01L 27/14
H01L 31/00
H01L 31/0232
H01L 31/0203
H01L 31/117

257431, 257432, 257434, 257435, 257437, 257443, 257444, 257446, 257448, 257449, 257450, 257453, 257457, 257458, 257459, 257461, 257616

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

8313662, Nov 20, 2012

Oct 1, 2009

12/572220

Philip Edward Miller - Livermore CA, US
Tayyab Ishaq Suratwala - Pleasanton CA, US
Jeffrey Devin Bude - Danville CA, US
Nan Shen - Fremont CA, US
William Augustus Steele - Tracy CA, US
Ted Alfred Laurence - Livermore CA, US
Michael Dennis Feit - Livermore CA, US
Lana Louie Wong - Pleasanton CA, US

Lawrence Livermore National Security, LLC - Livermore CA

B29D 11/00

216 24, 216 26, 216 97, 264 26, 264344

A method for preventing damage caused by high intensity light sources to optical components includes annealing the optical component for a predetermined period. Another method includes etching the optical component in an etchant including fluoride and bi-fluoride ions. The method also includes ultrasonically agitating the etching solution during the process followed by rinsing of the optical component in a rinse bath.

20060057825, Mar 16, 2006

Nov 8, 2005

11/269017

Jeffrey Bude - New Providence NJ, US
Malcolm Carroll - Albuquerque NM, US
Clifford King - New York NY, US

Agere Systems Inc. - Allentown PA

H01L 21/20
H01L 21/00

438481000, 438022000, 438073000, 438057000

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

20130139551, Jun 6, 2013

Dec 6, 2012

13/707053

Lawrence Livermore National Security, LLC - Livermore CA, US
Masoud BOLOURCHI - Livermore CA, US
Jeffrey D. BUDE - Danville CA, US
Gabriel M. GUSS - Manteca CA, US
Jeffery A. JARBOE - Livermore CA, US
Manyalibo J. MATTHEWS - Livermore CA, US
Michael C. NOSTRAND - Livermore CA, US
Paul J. WEGNER - Livermore CA, US

LAWRENCE LIVERMORE NATIONAL SECURITY, LLC - Livermore CA

C03C 23/00

65 28, 21912165

A method for repairing a damage site on a surface of an optical material is disclosed. The method may involve focusing an Infrared (IR) laser beam having a predetermined wavelength, with a predetermined beam power, to a predetermined full width (“F/W”) 1/ediameter spot on the damage site. The focused IR laser beam is maintained on the damage site for a predetermined exposure period corresponding to a predetermined acceptable level of downstream intensification. The focused IR laser beam heats the damage site to a predetermined peak temperature, which melts and reflows material at the damage site of the optical material to create a mitigated site.

56595042, Aug 19, 1997

May 25, 1995

8/450179

Jeffrey Devin Bude - New Providence NJ
Kevin John O'Connor - Lebanon NJ
Mark Richard Pinto - Morristown NJ

Lucent Technologies Inc. - Murray Hill NJ

G11C 1134

36518527

The invention is directed to a memory cell with a floating gate and a method for charging the floating gate using channel-initiated secondary electron injection (CISEI). In the device of the present invention, a positive bias voltage of about 1. 1 volts to about 3. 3 volts is applied between the drain and the source when introducing charge onto the floating gate. A negative bias voltage of about -0. 5 volts or more negative is applied to the substrate and the source. The drain substrate bias induces a sufficient amount of secondary hot electrons to be formed with a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate to charge the floating gate.

60117222, Jan 4, 2000

Oct 13, 1998

9/170819

Jeffrey Devin Bude - New Providence NJ
Marco Mastrapasqua - Annandale NJ

Lucent Technologies Inc. - Murray Hill NJ

G11C 1604

36518524

A method for programming and/or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices in a NOR array is disclosed. In the method, either a program verify or an erase verify is performed intermittently with the programming of a device or the erasure of the array. During the program-verify, one of either a negative V. sub. CS is applied to the deselected devices in the array, a negative V. sub. BS is applied to both the selected and deselected devices in the array, or both conditions are applied. Performing the program verify or erase verify in this manner is efficient and accurate. During the programming step, it is also advantageous if one of either a negative V. sub. CS is applied to the deselected devices in the array, a negative V. sub. BS is applied to the selected devices in the array, or both.