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Janardhanan S Ajit

from Saratoga, CA
Age ~57
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Also known as:
Janardhanan Sunitha Ajit, Janardhanan Shylaja Ajit, Janardhana S Ajit, Ajit S Janardhanan, Ajit Janardhana, Shylaja Janardhanan, Janardhanan Jit, Jit Janardhanan
Phone and address:
20760 4Th St, Saratoga, CA 95070
Connected to:
Abhishek Ajith, 32James G Ajith, 44John Ajith, 55Nishith Ajitsaria, 44De Ajja, 45Rosemarie Ajjan, 55Venkata M Ajjarapu, 53Daniel G Ajjouri, 34Karissa I Ajlouny, 34Peter O Ajlouny, 55

Janardhanan Ajit Phones & Addresses

  • 20760 4Th St, Saratoga, CA 95070
  • College Station, TX
  • Austin, TX
  • 455 Costa Mesa Ter, Sunnyvale, CA 94085 (408) 774-9670
  • 455 Costa Mesa Ter #E, Sunnyvale, CA 94085
  • 67 Figtree, Irvine, CA 92603
  • 12 Woodrush, Irvine, CA 92604 (949) 786-0094
  • Redondo Beach, CA
  • Durham, NH
  • Santa Clara, CA
  • PO Box 52933, Irvine, CA 92619

Work

Position: Protective Service Occupations

Publications

Us Patents

Slew-Rate-Control Structure For High-Frequency Operation

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US Patent:
6359484, Mar 19, 2002
Filed:
Jul 19, 2000
Appl. No.:
09/618961
Inventors:
Janardhanan S. Ajit - Sunnyvale CA
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03K 512
US Classification:
327170
Abstract:
The present invention provides an integrated circuit driver having multiple resistance paths that switch on at different stages of the rising and falling transitions of the drivers output signal waveform. The driver also has a control circuit configured to turn on the one or more resistance paths during at least one predetermined stage of the output signal during transitions, thus reducing the control circuits effective resistance to control the slope of the transitions during the predetermined stage.

Esd Structure For Ic With Over-Voltage Capability At Pad In Steady-State

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US Patent:
6424510, Jul 23, 2002
Filed:
Apr 28, 2000
Appl. No.:
09/560632
Inventors:
Janardhanan S. Ajit - Sunnyvale CA
Hung Pham Le - San Jose CA
Assignee:
Exar Corporation - Fremont CA
International Classification:
H02H 900
US Classification:
361 59, 361 911, 361111, 361127
Abstract:
The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source. The second voltage divider has a node connected to a gate of the second NMOS transistor.

High-Voltage Transistor With Multi-Layer Conduction Region

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US Patent:
6570219, May 27, 2003
Filed:
May 17, 2000
Appl. No.:
09/574563
Inventors:
Vladimir Rumennik - Los Altos CA
Donald R. Disney - Cupertino CA
Janardhanan S. Ajit - Sunnyvale CA
Assignee:
Power Integrations, Inc. - San Jose CA
International Classification:
H01L 2976
US Classification:
257343, 257262, 257335, 257336, 257342
Abstract:
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Methods And Systems For Limiting Supply Bounce

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US Patent:
6608519, Aug 19, 2003
Filed:
Jun 28, 2002
Appl. No.:
10/183450
Inventors:
Janardhanan S. Ajit - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 508
US Classification:
327379, 326 87
Abstract:
Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Sub-Micron High Input Voltage Tolerant Input Output (I/O) Circuit

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US Patent:
6628149, Sep 30, 2003
Filed:
Jan 9, 2002
Appl. No.:
10/043788
Inventors:
Janardhanan S. Ajit - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B 100
US Classification:
327108, 327333, 326 81, 326 83, 326 86
Abstract:
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

High-Voltage Transistor With Multi-Layer Conduction Region

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US Patent:
6633065, Oct 14, 2003
Filed:
Sep 20, 2001
Appl. No.:
09/961221
Inventors:
Vladimir Rumennik - Los Altos CA
Donald R. Disney - Cupertino CA
Janardhanan S. Ajit - Sunnyvale CA
Assignee:
Power Integrations, Inc. - San Jose CA
International Classification:
H01L 31113
US Classification:
257342, 257343, 257341, 257262
Abstract:
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

High-Voltage Transistor With Multi-Layer Conduction Region

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US Patent:
6639277, Oct 28, 2003
Filed:
Sep 20, 2001
Appl. No.:
09/961235
Inventors:
Valdimir Rumennik - Los Altos Hills CA
Donald R. Disney - Cupertino CA
Janardhanan S. Ajit - Sunnyvale CA
Assignee:
Power Integrations, Inc. - San Jose CA
International Classification:
H01L 2976
US Classification:
257342, 257339, 257343, 257492
Abstract:
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Delay Circuit With Delay Relatively Independent Of Process, Voltage, And Temperature Variations

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US Patent:
6646488, Nov 11, 2003
Filed:
Jun 27, 2002
Appl. No.:
10/180501
Inventors:
Janardhanan S. Ajit - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03H 1126
US Classification:
327262, 327263
Abstract:
Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (âPVTâ) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.
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Janardhanan S Ajit from Saratoga, CA, age ~57 Get Report