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James Ching Yik

from Laguna Niguel, CA
Age ~57

James Yik Phones & Addresses

  • 24565 Palace Ct, Laguna Niguel, CA 92677
  • 20917 Fuerte Dr, Walnut, CA 91789 (949) 472-0874
  • Playa del Rey, CA
  • 21011 Stoney Gln, Lake Forest, CA 92630 (949) 498-6540
  • 21001 Stoney Gln, Lake Forest, CA 92630
  • 24682 Vesta, Mission Viejo, CA 92691 (949) 472-0874 (949) 498-6540
  • 2482 Vesta, Mission Viejo, CA 92690 (714) 472-0874
  • Covina, CA
  • Orange, CA
  • 24565 Palace Ct, Laguna Niguel, CA 92677 (949) 735-2298

Work

Position: Technicians and Related Support Occupations

Education

Degree: Bachelor's degree or higher

Publications

Us Patents

Internal Communication Protocol For Data Switching Equipment

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US Patent:
7082138, Jul 25, 2006
Filed:
Sep 28, 2001
Appl. No.:
09/966691
Inventors:
James Ching-Shau Yik - Mission Viejo CA, US
Linghsiao Wang - Tustin CA, US
Assignee:
Zarlink Semiconductor V.N. Inc. - Irvine CA
International Classification:
A04L 12/56
G06F 3/00
G06F 13/00
US Classification:
370410, 710 21, 710100
Abstract:
A protocol enabling the exchange of information between data switching node components and a supervisory management processor is provided. The protocol defines a data frame format, data fields, data field values of a group of command frames. The exchange of information therebetween via the defined frames enables the production of data switching equipment having a generic implementation with a deployable, upgradeable and expandable feature set providing and enhancing support for current and future services.

Time-Indexed Multiplexing As An Efficient Method Of Scheduling In Hardware

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US Patent:
7085704, Aug 1, 2006
Filed:
May 7, 2002
Appl. No.:
10/139644
Inventors:
James Yik - Mission Viejo CA, US
Craig Barrack - Irvine CA, US
Assignee:
Zarlink Semicorporation V.N. Inc. - Irvine CA
International Classification:
G06F 9/44
H04L 12/28
US Classification:
703 19, 709226, 370230, 3703954, 700 99, 718105
Abstract:
Methods and apparatus for hardware scheduling processes handling are presented. The apparatus includes a table of task lists. Each task list has specifications of processes requiring handling during a corresponding time interval. Each task list is parsed by a scheduler during a corresponding interval and the processes specified therein are handled. The methods of process handling may include a determination of a next time interval in which the process requires handling and inserting of process specifications in task lists corresponding to the determined next handling times. Implementations are also presented in which task lists specify work units requiring handling during corresponding time intervals. The entire processing power of the scheduler is used to schedule processes for handling. Advantages are derived from an efficient use of the processing power of the scheduler as the number of processes is increased.

Hardware Implementation Of Voice-Over-Ip Playback With Support For Comfort Noise Insertion

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US Patent:
7142551, Nov 28, 2006
Filed:
Jul 15, 2002
Appl. No.:
10/195657
Inventors:
Craig Barrack - Irvine CA, US
James Yik - Mission Viejo CA, US
Assignee:
Zarlink Semiconductor V.N. Inc. - Irvine CA
International Classification:
H04L 12/28
US Classification:
370412, 370468
Abstract:
Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.

Method Of Pacing The Synchronization Of Routing Information In A Data Switching Environment

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US Patent:
7257134, Aug 14, 2007
Filed:
Oct 3, 2001
Appl. No.:
09/969702
Inventors:
James Ching-Shau Yik - Mission Viejo CA, US
Eric Lin - Hacienda Heights CA, US
Assignee:
Zarlink Semiconductor V.N. Inc. - Irvine CA
International Classification:
H04J 3/06
H04L 12/66
H04L 12/56
G06F 15/173
US Classification:
370509, 370352, 370389, 370511, 370503, 709223
Abstract:
A method of synchronizing the information held in a switching database associated with a switching function of a data switching node, with a data network node identifier record associated with a management processor enabling a managed mode thereof is provided. An entry of the switching database is modified. A status specifier corresponding to the modified entry is set to signify the modification thereof. An inspection of the switching database is initiated on the expiration of an adjustable timer, and the information held in modified switching database entries is synchronized with the data network node identifier record. This method of synchronization of the information held in the switching database spreads out of burst changes thereof over time. The advantages are derived from the use of a more economical management processor while providing the same or enhanced levels of service of the data switching node.

Apparatus For Link Failure Detection On High Availability Ethernet Backplane

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US Patent:
7260066, Aug 21, 2007
Filed:
Dec 20, 2002
Appl. No.:
10/326352
Inventors:
Linghsiao Wang - Irvine CA, US
Eric Lin - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US
Assignee:
Conexant Systems, Inc. - Red Bank NJ
International Classification:
G01R 31/08
US Classification:
370248, 370249
Abstract:
A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

High-Speed Mac Address Search Engine

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US Patent:
7373425, May 13, 2008
Filed:
Dec 31, 2003
Appl. No.:
10/750445
Inventors:
Craig Barrack - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US
Eric Lin - Irvine CA, US
Assignee:
Conexant Systems, Inc. - Red Bank NJ
International Classification:
G06F 15/173
G06F 15/16
US Classification:
709238, 709245, 709247
Abstract:
Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Combined Pipelined Classification And Address Search Method And Apparatus For Switching Environments

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US Patent:
7760719, Jul 20, 2010
Filed:
Jun 30, 2004
Appl. No.:
10/881226
Inventors:
James Yik - Mission Viejo CA, US
Eric Lin - Irvine CA, US
John Ta - Laguna Niguel CA, US
Craig Barrack - Irvine CA, US
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H04L 12/28
US Classification:
370389, 370392, 37039542
Abstract:
A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

High Availability Ethernet Backplane Architecture

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US Patent:
7835265, Nov 16, 2010
Filed:
Oct 31, 2002
Appl. No.:
10/284856
Inventors:
Linghsiao Wang - Irvine CA, US
Eric (Changhwa) Lin - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 11/00
H04L 12/28
US Classification:
370216, 370245, 370248, 370338, 370392, 3703952, 709223, 709231, 709238, 709242
Abstract:
A high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. The node boards and the switch fabric boards routinely perform link integrity checks when operating in a normal mode such that each can independently initiate failover to working ports when a link failure is detected. Link failure is detected either by sending a link heartbeat message after the link has had no traffic for a predetermined interval, or after receiving a predetermined consecutive number of invalid packets. Once the link failure is resolved, operation resumes in normal mode.
James Ching Yik from Laguna Niguel, CA, age ~57 Get Report