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James J Vorgert

from Celeste, TX
Age ~61
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Also known as:
James Joseph Vorgert, James S Vorgert, Jim J Vorgert
Related to:
Claudia M Vorgert, 93Elvina Folse, 39Heath Folse, 43Steven Folse, 75Marianne Johnson, 59Dreau Folse, 32
Connected to:
Mary Vorgert, 70Tina M Vorgia, 64Steven Vorgias, 65Jason S Vorhaben, 53Tessa P Vorhaben, 42Julianna L Vorhaus, 40Michael J Vorhease, 43Charles B Vorhees, 39Curtis M Vorhees, 47Amy E Vorheis, 43

James Vorgert Phones & Addresses

  • Celeste, TX
  • 6104 Belle Ct, Mc Kinney, TX 75070 (214) 726-0960 (972) 547-0076
  • McKinney, TX
  • 1913 Smith Rd, Plano, TX 75023 (972) 517-6549
  • Dallas, TX
  • Hunt, TX

Work

Company: Crossfield technology llc Jul 2017 Position: Senior engineer

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: University of Minnesota 1981 to 1986 Specialities: Architecture

Skills

Fpga • Asic • Semiconductors • Analog • Ic • Vhdl • Embedded Systems • Microcontrollers • Timing Closure • Soc • Actel • Mixed Signal • Application Specific Integrated Circuits • Hardware Architecture • Rf • Field Programmable Gate Arrays • Eda • Xilinx • Product Management • Semiconductor Industry • Arm • Verilog • Processors • Integrated Circuit Design • Modelsim • Vlsi • Integrated Circuits

Interests

Violinist • Rock Climbing • Camping/Hiking • Ameteur Radio • Photography • Story Telling • Woodworking

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

James Vorgert Photo 1

Senior Engineer

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Location:
5370 County Rd, Celeste, TX
Industry:
Electrical/Electronic Manufacturing
Work:
Crossfield Technology Llc
Senior Engineer
Microsemi Corporation Jan 1, 2002 - May 2017
Area Technical Manager
Nokia May 1995 - Dec 2001
Field Applications Engineer - Orca
Texas Instruments Sep 1986 - May 1995
Design Engineer
Education:
University of Minnesota 1981 - 1986
Bachelors, Bachelor of Science In Electrical Engineering, Architecture
Skills:
Fpga
Asic
Semiconductors
Analog
Ic
Vhdl
Embedded Systems
Microcontrollers
Timing Closure
Soc
Actel
Mixed Signal
Application Specific Integrated Circuits
Hardware Architecture
Rf
Field Programmable Gate Arrays
Eda
Xilinx
Product Management
Semiconductor Industry
Arm
Verilog
Processors
Integrated Circuit Design
Modelsim
Vlsi
Integrated Circuits
Interests:
Violinist
Rock Climbing
Camping/Hiking
Ameteur Radio
Photography
Story Telling
Woodworking

Publications

Us Patents

Method For In-System Programming Of Serially Configured Eeproms Using A Jtag Interface Of A Field Programmable Gate Array

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US Patent:
61377384, Oct 24, 2000
Filed:
Nov 30, 1999
Appl. No.:
9/452017
Inventors:
James Joseph Vorgert - Plano TX
Assignee:
Lucent Technologies, Inc. - Murray Hill NJ
International Classification:
G11C 2900
US Classification:
365201
Abstract:
A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board. The EEPROM is used as a memory storage device for a field programmable gate array (FPGA), which is mounted on the printed circuit board. The board and FPGA have a joint test action group (JTAG) test interface. The FPGA contains a test access port (TAP) and user defined internal scan registers. The method includes providing a connection between the TAP of the FPGA and the EEPROM. Data is provided to the internal scan data registers of the FPGA via the JTAG test interface. Data is transferred via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.

Auto Focus System For A Slm Based Image Display System

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US Patent:
62464469, Jun 12, 2001
Filed:
Jun 10, 1997
Appl. No.:
8/872634
Inventors:
Scott Heimbuch - Dallas TX
James Vorgert - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 574
US Classification:
348750
Abstract:
An image display system (10) having an auto-focus system (24). An image sensor (20) such as a CCD camera, senses the sharpness of pixels (26) comprising a portion of the image at a screen (16), preferably a magnified portion of the image. A sensor data processor (22) processes the pixel data from the sensor (20), and instructs the auto focus system (24) to adjust an optical parameter such as the focal length of a projector lens (14) as a function of the sensor (20) output. A DMD-type SLM is preferably utilized due to the uniform geometric features of the pixel mirrors, but other SLM's can be used. The sharpness or contrast between an "on" and an "off" pixel is sensed, and preferably a 10. times. 10 array of pixels arranged in a checker board pattern is sensed.
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James J Vorgert from Celeste, TX, age ~61 Get Report