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James M Katana

from Bend, OR
Age ~83
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Also known as:
James Michael Katana, Jim M Katana
Phone and address:
21660 Coyote Dr, Bend, OR 97702
(541) 389-8043
Related to:
Stephanie Katana, 44Lois L Katana, 75Christopher J Katana, 43
Connected to:
Colleen D Katana, 41John M Katana, 44Laureen A Katana, 60Smith Katana, 38Kamel A Katanani, 47Dheeraj Katangur, 51Mrudula R Katanguru, 45Suzanne E Katanic, 50Ryan S Katano, 33Jacob Katanov, 49

James Katana Phones & Addresses

  • 21660 Coyote Dr, Bend, OR 97702 (541) 389-8043
  • Santa Clara, CA
  • 21660 Coyote Dr, Bend, OR 97702

Work

Position: Service Occupations

Education

Degree: Associate degree or higher

Emails

j***[email protected]

Publications

Us Patents

Igbt Process To Produce Platinum Lifetime Control

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US Patent:
5190885, Mar 2, 1993
Filed:
Mar 13, 1992
Appl. No.:
7/852932
Inventors:
Do Pik - Bend OR
Dah W. Tsang - Bend OR
James M. Katana - Bend OR
Assignee:
Advanced Power Technology, Inc. - Bend OR
International Classification:
H01L 2100
H01L 2102
H01L 21467
US Classification:
437 31
Abstract:
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (. about. 10. sup. 14 /cm. sup. 3) to block reverse bias voltage. The N+ layer is >20. mu. m thick and doped below. about. 10. sup. 17 /cm. sup. 3 but above the N- doping to enhance output impedance and reduce gain at high V. sub. ce conditions. Or the N+ layer is formed with a thin (. about. 5. mu. m) highly doped (>10. sup. 17 /cm. sup. 3) layer and a thick (>20. mu. m) layer of. about. 10. sup. 16 /cm. sup. 3 doping. A platinum dose of 10. sup. 13 to 10. sup. 16 /cm. sup. 2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

High Reliability-High Voltage Junction Termination With Charge Dissipation Layer

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US Patent:
8476691, Jul 2, 2013
Filed:
Feb 18, 2011
Appl. No.:
13/030907
Inventors:
Dumitru Sdrulla - Bend OR, US
Duane Edward Levine - Bend OR, US
James M. Katana - Bend OR, US
Martin David Birch - Louisville CO, US
Assignee:
Microsemi Corporation - Bend OR
International Classification:
H01L 21/336
H01L 29/78
US Classification:
257315, 257314, 257324, 257E27103, 257E29302, 257E21682, 438131, 438257, 438287
Abstract:
A high voltage power semiconductor device includes high reliability-high voltage junction termination with a charge dissipation layer. An active device area is surrounded by a junction termination structure including one or more regions of a polarity opposite the substrate polarity. A tunneling oxide layer overlays the junction termination area surrounding the active device area in contact with the silicon substrate upper surface. A layer of undoped polysilicon overlays the tunneling oxide layer and spans the junction termination area, with connections to an outer edge of the junction termination structure and to a grounded electrode inside of the active area. The tunneling oxide layer has a thickness that permits hot carriers formed at substrate upper surface to pass through the tunneling oxide layer into the undoped polysilicon layer to be dissipated but sufficient to mitigate stacking faults at the silicon surface.

Igbt Device With Platinum Lifetime Control Having Gradient Or Profile Tailored Platinum Diffusion Regions

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US Patent:
52832023, Feb 1, 1994
Filed:
Sep 15, 1992
Appl. No.:
7/945817
Inventors:
Douglas A. Pike - Bend OR
Dah W. Tsang - Bend OR
James M. Katana - Bend OR
Assignee:
Advanced Power Technology, Inc. - Bend OR
International Classification:
H01L 2100
H01L 2102
H01L 21265
H01L 21467
US Classification:
437 31
Abstract:
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (. about. 10. sup. 14 /cm. sup. 3) to block reverse bias voltage. The N+ layer is >20. mu. m thick and doped below. about. 10. sup. 17 /cm. sup. 3 but above the N- doping to enhance output impedance and reduce gain at high V. sub. ce conditions. Or the N+ layer is formed with a thin (. about. 5. mu. m) highly doped (>10. sup. 17 /cm. sup. 3) layer and a thick (>20. mu. m) layer of. about. 10. sup. 16 /cm. sup. 3 doping. A platinum dose of 10. sup. 13 to 10. sup. 16 /cm. sup. 2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Igbt Device With Platinum Lifetime Control And Reduced Gaw

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US Patent:
55280587, Jun 18, 1996
Filed:
Oct 13, 1994
Appl. No.:
8/329974
Inventors:
Douglas A. Pike - Bend OR
Dah W. Tsang - Bend OR
James M. Katana - Bend OR
Dumitru Sdrulla - Bend OR
Assignee:
Advanced Power Technology, Inc. - Bend OR
International Classification:
H01L 2974
H01L 31111
US Classification:
257142
Abstract:
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (. about. 10. sup. 14 /cm. sup. 3) to block reverse bias voltage. The N+ layer is >20. mu. m thick and doped below. about. 10. sup. 17 /cm. sup. 3 but above the N- doping to enhance output impedance and reduce gain at high V. sub. ce conditions. Or the N+ layer is formed with a thin (. about. 5. mu. m) highly doped (>10. sup. 17 /cm. sup. 3) layer and a thick (>20. mu. m) layer of. about. 10. sup. 16 /cm. sup. 3 doping. A platinum dose of 10. sup. 13 to 10. sup. 16 /cm. sup. 3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Igbt Process To Produce Platinum Lifetime Control

View page
US Patent:
52623360, Nov 16, 1993
Filed:
Mar 13, 1992
Appl. No.:
7/852932
Inventors:
Douglas A. Pike - Bend OR
Dah W. Tsang - Bend OR
James M. Katana - Bend OR
Assignee:
Advanced Power Technology, Inc. - Bend OR
International Classification:
H01L 2100
H01L 2102
H01L 21467
US Classification:
437 31
Abstract:
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (. about. 10. sup. 14 /cm. sup. 3) to block reverse bias voltage. The N+ layer is >20. mu. m thick and doped below. about. 10. sup. 17 /cm. sup. 3 but above the N- doping to enhance output impedance and reduce gain at high V. sub. ce conditions. Or the N+ layer is formed with a thin (. about. 5. mu. m) highly doped (>10. sup. 17 /cm. sup. 3) layer and a thick (>20. mu. m) layer of. about. 10. sup. 16 /cm. sup. 3 doping. A platinum dose of 10. sup. 13 to. about. 10. sup. 16 /cm. sup. 2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.
Control profile
James M Katana from Bend, OR, age ~83 Get Report