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Jaehong Chon

from San Diego, CA
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Also known as:
Jae Hong Chon
Phone and address:
7712 Marker Rd, San Diego, CA 92130
Connected to:
Andrew J Chon, 50Chong Chon, 47Eugene G Chon, 33Hesun L Chon, 48Jaime Chon, 33Jason C Chon, 63Joseph S Chon, 50Justine H Chon, 54Lee R Chon, 47Mike Chon, 52

Jaehong Chon Phones & Addresses

  • 7712 Marker Rd, San Diego, CA 92130
  • Mountain View, CA
  • Seattle, WA

Work

Company: Qualcomm Oct 2011 Address: Greater San Diego Area Position: Staff engineer

Education

Degree: Ph. D. School / High School: University of Washington 2007 to 2011 Specialities: Electrical Engineering

Skills

Image Processing • H.264 • C++ • C • Video Coding • Lte • Digital Signal Processors • Signal Processing • Telecommunications • Mobile Devices • Cellular • Wireless • Algorithms • Software Development • Dsp • Embedded Systems • Hevc • Video Conferencing • Embedded Software • Cellular Communications

Interests

Swimming • Ski • Tennis

Industries

Telecommunications

Resumes

Resumes

Jaehong Chon Photo 1

Video Architect

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Location:
459 Burgoyne St, Mountain View, CA 94043
Industry:
Telecommunications
Work:
Qualcomm - Greater San Diego Area since Oct 2011
Staff Engineer
University of Washington - Greater Seattle Area Mar 2007 - Oct 2011
Research Assistant
Apple Inc. Jun 2009 - Sep 2009
Summer Intern
Samsung Electronics Feb 1998 - Dec 2006
Senior Engineer
Education:
University of Washington 2007 - 2011
Ph. D., Electrical Engineering
Skills:
Image Processing
H.264
C++
C
Video Coding
Lte
Digital Signal Processors
Signal Processing
Telecommunications
Mobile Devices
Cellular
Wireless
Algorithms
Software Development
Dsp
Embedded Systems
Hevc
Video Conferencing
Embedded Software
Cellular Communications
Interests:
Swimming
Ski
Tennis

Publications

Us Patents

Merge Signaling And Loop Filter On/Off Signaling

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US Patent:
20130258049, Oct 3, 2013
Filed:
Mar 14, 2013
Appl. No.:
13/829774
Inventors:
Jaehong Chon - San Diego CA, US
Marta Karczewicz - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04N 7/26
US Classification:
348 42, 37524002
Abstract:
Systems, methods, and devices are disclosed that encode video, decode video, or both. These systems, methods, and devices generate and/or receive an enable syntax element in an encoded bitstream, wherein the enable syntax element indicates whether a loop filter is turned on or turned off for a group of video blocks. They also generate or receive one or more additional syntax elements identifying parameters for the loop filter for the group of video blocks in response to the enable syntax element indicating the loop filter is turned on for the group of video blocks. These systems, methods, and devices also perform the loop filter for the group of video blocks based on the received enable syntax element.

Adaptive Quantizer Design For Video Coding

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US Patent:
20210400273, Dec 23, 2021
Filed:
Apr 19, 2021
Appl. No.:
17/234596
Inventors:
- Cupertino CA, US
Jaehong CHON - Cupertino CA, US
Alexandros TOURAPIS - Milpitas CA, US
David W. SINGER - San Francisco CA, US
International Classification:
H04N 19/124
H04N 19/82
H04N 19/186
H04N 19/172
Abstract:
Improved video coding and decoding techniques are described, including techniques to derive quantization step sizes adaptively with quantization step size table templates. Quantization techniques described provide finer-grained control over quantization with a more flexible quantization step size especially at higher degrees of quantization. This may result in improved overall compression quality. Other coding parameters, such as in-loop filtering parameters, may be derived based on the more flexible quantization parameters.

Adaptive Mode Checking Order For Video Encoding

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US Patent:
20160261861, Sep 8, 2016
Filed:
Jun 11, 2015
Appl. No.:
14/737252
Inventors:
- San Diego CA, US
Wei-Jung Chien - San Diego CA, US
Xianglin Wang - San Diego CA, US
Jaehong Chon - San Diego CA, US
In Suk Chong - San Diego CA, US
Marta Karczewicz - San Diego CA, US
Woo-Shik Kim - San Diego CA, US
Xin Zhao - San Diego CA, US
International Classification:
H04N 19/103
H04N 19/567
Abstract:
A video encoding device comprises a memory configured and at least one processor configured to: determine whether a metric meets a condition based on statistics, wherein the statistics are associated with a first video encoding mode checking order and a second video encoding mode checking order, responsive to determining that the metric meets the condition, select a first encoding mode checking order to encode the first block of video data responsive to determining that the condition is not met, select a second encoding mode checking order different from the first encoding mode checking order to encode the first block of video data, update the statistics based on the selected first or second encoding mode checking order, and encode a second block of video data, based on the updated statistics, and using the first or second mode checking order.

Fast Video Encoding Method With Block Partitioning

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US Patent:
20160261870, Sep 8, 2016
Filed:
Jun 11, 2015
Appl. No.:
14/737271
Inventors:
- San Diego CA, US
Wei-Jung Chien - San Diego CA, US
Xianglin Wang - San Diego CA, US
Jaehong Chon - San Diego CA, US
In Suk Chong - San Diego CA, US
Marta Karczewicz - San Diego CA, US
Woo-Shik Kim - San Diego CA, US
Xin Zhao - San Diego CA, US
International Classification:
H04N 19/147
H04N 19/14
H04N 19/174
H04N 19/176
Abstract:
A video encoding device comprises a memory configured to store video data and at least one processor configured to: select one of a full rate-distortion (RD) checking scheme or a fast RD checking scheme, determine an RD cost associated with encoding a block of the video data based on the selected full RD checking scheme or fast RD checking scheme, determine a partitioning scheme for the block based on the determined RD cost, and encode the block using the determined partitioning scheme based on the determined RD cost.
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Jaehong Chon from San Diego, CA Get Report