Jacob Ben Avidan

6467074, Oct 15, 2002

Mar 21, 2000

09/532330

Athanassios Katsioulas - San Jose CA
Stan Chow - Los Altos CA
Jacob Avidan - Los Altos CA
Dimitris Fotakis - Sunnyvale CA

Ammocore Technology, Inc.

G06F 1750

716 17, 716 8

An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture forms a layout that includes a plurality of STANDARD BLOCKs, top-level cells, and hard IP blocks. The STANDARD BLOCKS form row-based or column-based STANDARD BLOCK ARRAY configurations in which STANDARD BLOCKs are placed adjacent to each other in a row or column configuration with their fixed or quantized dimension aligned and oriented perpendicular to the STANDARD BLOCK ARRAY direction. Individual STANDARD BLOCK ARRAYs can be spaced apart forming channels between them to allow for routing interconnections, or overlapping one another in a flipped configuration sharing VDD or GND power rails. The IC layout includes sites reserved for top-level cells that are placed in channels between STANDARD BLOCK ARRAYs, around the perimeter of STANDARD BLOCKs, or arranged in a staggered or diagonal configuration inside the STANDARD BLOCKs. The layout of the IC further includes power grid and clock grid structures providing, respectively, power and ground and clock distribution. Each of the STANDARD BLOCKs has a form that is physically constrained such that its dimensions feature one fixed or quantized dimension, and one variable dimension that ranges between predefined limits; a granularity larger than a standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells; and flexible physical design properties.

6536028, Mar 18, 2003

Mar 14, 2000

09/525184

Athanassios Katsioulas - San Jose CA
Stan Chow - Los Altos CA
Jacob Avidan - Los Altos CA
Dimitris Fotakis - Sunnyvale CA

Ammocore Technologies, Inc. - Santa Clara CA

G06F 1750

716 17, 716 7

A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general physical abstractions such that each STANDARD BLOCK is akin to a black box model with the majority of its internal design aspects invisible to the top-level assembly tool while selected design aspects remain visible.

7971168, Jun 28, 2011

May 29, 2008

12/128919

Robert Swanson - Palo Alto CA, US
Jacob Avidan - Los Altos CA, US
Roger Carpenter - Palo Alto CA, US

Magna Design Automation, Inc. - San Jose CA

G06F 17/50

716113, 716108, 716134

In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e. g. , impact to schedule, CPU/memory resources, ECOs).

8407650, Mar 26, 2013

May 30, 2008

12/129916

Jacob Avidan - Los Altos CA, US
Sandeep Grover - Sunnyvale CA, US
Roger Carpenter - Palo Alto CA, US
Philippe Sarrazin - San Jose CA, US

Synopsis, Inc. - Mountain View CA

G06F 17/50

716129, 716126

In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

20070245281, Oct 18, 2007

Apr 12, 2007

11/734757

Michael Riepe - San Jose CA, US
Niranjana Balasundaram - Newark CA, US
Menno Verbeek - JIM Utrecht, NL
Hong Cai - Redwood City CA, US
Roger Carpenter - Palo Alto CA, US
Jacob Avidan - Los Altos CA, US

G06F 17/50
G06F 9/45

716009000, 716007000

A method and system for performing placement-driven physical hierarchy generation in the context of an integrated circuit layout generation system is provided. This generation optimizes the physical hierarchy to improve placement of the cells in the layout, and the associated interconnect routability and delay. A new pre-clustering phase is introduced to maintain as much of the input logical hierarchy as possible while maintaining physical hierarchy quality. And a new cost function is described which is based on measuring the mutual affinity of cells in a virtually-flat placement. The new cost function is used during the new pre-clustering phase, as well as the common clustering, partitioning, and declustering/refinement phases of physical hierarchy generation.

61580228, Dec 5, 2000

Apr 13, 1998

9/059596

Jacob Avidan - Los Altos CA

Synopsys, Inc. - Mountain View CA

G06F 1300
G06F 1100
G01R 3128

714 33

A circuit analyzer, adapted to run in the memory of a processing system, for characterizing the performance of a circuit under test. The circuit analyzer of the present invention obviates traditional design steps by using gray and transparent circuit elements in addition to the traditional black circuit elements.

57403473, Apr 14, 1998

May 1, 1995

8/429430

Jacob Avidan - Los Altos CA

Synopsys, Inc. - Mountain View CA

G06F 1300

39518309

A method, apparatus and medium containing a computer program for analyzing timing in circuits. In one embodiment, the invention sets the direction of elements of a circuit by partitioning the circuit to identify a subcircuit including a pullup or pulldown block, then modeling the subcircuit as a single transistor, then setting the direction of that single transistor and then propagating the direction of that single transistor to other elements of the subcircuit. In another embodiment, the invention generates a gray box model by searching paths from a primary clock input of a circuit, determining worst and best paths among the multiple elements of the circuit and incorporating the best and worst path information in the gray box model. In another embodiment, the invention instantiates such a gray box model in a second circuit and performs timing checks on this second circuit.