Ivailo M Nedelchev

6480815, Nov 12, 2002

May 10, 1999

09/309479

Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA
Ashutosh S. Mauskar - Sunnyvale CA

Synopsys, Inc. - Mountain View CA

G06F 1750

703 14, 703 18, 703 20, 716 17, 716 18

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell âlibraryâ within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e. g. , input pin) caused the designated pin to transition.

59034769, May 11, 1999

Oct 29, 1996

8/739219

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Synopsys, Inc. - Mountain View CA

G06F17/50

364578

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

61956309, Feb 27, 2001

May 10, 1999

9/309485

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Synopsys, Inc. - Mountain View CA

G06F 1750

703 18

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

59496894, Sep 7, 1999

Oct 29, 1996

8/739311

Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Danny Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA
Ashutosh S. Mauskar - Sunnyvale CA

Synopsys, Inc. - Mountain View CA

G06F 1750

364488

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e. g. , input pin) caused the designated pin to transition.

58385797, Nov 17, 1998

Oct 29, 1996

8/740502

Janet Olson - Saratoga CA
Ivailo Nedelchev - Santa Clara CA
Yuegin Danny Lin - Sunnyvale CA
Ashutosh S. Mauskar - Sunnyvale CA
James Sproch - Saratoga CA

Synopsys, Inc. - Mountain View CA

G06F 1750

364488

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular pin (e. g. , input, output, bidirectional, internal) based on a prescribed condition of the state of signals that exist contemporaneously with a signal transition on the particular pin. This is referred to as state dependent power modeling. A different power consumption value can be provided for each different modeled state. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. State dependent power modeling of the present invention allows library designers to specify a different set of power values depending on the condition of one or more pins of the library cell (e. g. , the library's representation of the logic cell).